Sentinel-SSO

ANSYS Sentinel-SSO is an I/O DDR power noise and timing analysis solution targeted for chip (I/O), package and system engineers. It enables optimization of I/O and package/PCB designs to minimize both jitter and the impact of power/ground noise on DDR signal propagation.


  Watch the video below to learn how Sentinel-SSO, the signal and power integrity solution for high-speed DDR/IO, enables fast, accurate and holistic simulation of the entire DDR subsystem.

Designers who use Sentinel-SSO can perform a time-domain simulation of an entire DDR interface channel, including the bank of DDR buffers, on- and off-chip decoupling capacitors, and on-chip, package and PCB interconnect parasitics. The software accurately predicts the impact of simultaneously switching noise on signal propagation and ensuing jitter. Thanks to its rich GUI and seamless work-flow, Sentinel-SSO offers guidance and root-cause analysis on power hot-spots. It also helps users to identify and resolve design issues that contribute to higher power/ground noise and jitter.

As parallel DDR interfaces increase in bit width, delivering transistor-level accuracy while simulating the entire I/O bank — along with all the associated parasitic and decaps in chip, package and PCB — becomes more challenging. Traditional SPICE approaches lack capacity to resolve issues, while conventional I/O models lack required accuracy. Sentinel-SSO uses proprietary modeling techniques that help you to meet competing needs for full-I/O bank capacity and transistor-level accuracy.


Comparison of victim, VDD and GND noise on DDR I/O bank using different modeling techniques

Sentinel-SSO creates I/O buffer models and on-die signal and power routing by using the I/O layout information provided through direct data import or ANSYS RedHawk. Models accurately capture the nonlinear, physical nature of underlying circuits in a compact, SPICE-friendly format; their validity and the compactness enable full-I/O bank simulation, provide package and PCB parasitics, and maintain required transistor-level accuracy.

Sentinel-SSO’s seamless setup, simulation flow and result analysis provides relevant information quickly and efficiently; it also allows for real-time interactive design fixing and optimization. Package SI/PI engineers use our tools to identify and fix on-chip power delivery network (PDN) routing issues as well as to perform package-level editing and what-if analysis.

The integrated reporting capability makes it easy to generate waveform comparisons, eye diagrams and JEDEC parameter reports. Sentinel-SSO supports industry-standard SPICE simulators, including HSPICE, Spectre and Eldo.


Integrating multi-pane Sentinel-SSO graphical user interface


Sentinel-SSO on ansys.com