- Products
- RedHawkSoC Dynamic Power, Advanced Low Power, Reliability, and Chip-Package Co-design
- PowerArtistRTL Power Reduction, Analysis, Debug, and RPM Generation
- TotemAnalog/Mixed-Signal Dynamic Power, Substrate Noise, EM, and ESD
- PathFinderESD Planning, Verification and Sign-off
- Sentinel-SSOI/O DDR Power Noise and Timing Analysis
- Sentinel-TIThermal Simulation and Mechanical Stress Integrity Analysis
- Supported Platforms
- ResourcesTechnical Papers, Presentations, Contributed Articles,Conference Papers, Webinars, Videos
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Achieve Faster IC Power Closure Using Streamlined Chip–Package Co-Analysis
This webinar shows how RedHawk-CPA and its unified environment perform DC, transient and AC power-integrity analysis
FinFET-Based Designs: Package Model Considerations
3D transistors improve performance and reduce energy consumption, but they also add new design challenges.
FinFET-Based Designs: Power Sign-off Considerations
An accurate, distributed package model is required to ensure sign-off quality results.
FinFET-Based Designs: Power Analysis Considerations
The use of FinFET introduces additional challenges and increases existing ones, especially with power budgeting, voltage drop, EM and overall power noise reliability sign-off.
How to Use RedHawk 2014 for Power Noise and Reliability Sign-off in FinFET Designs
This webinar covers new capabilities in RedHawk that enable power noise and reliability sign-off for large FinFET based designs.
In The News
Apr
9
The Wild West Of Automotive - Semiconductor Engineering
Mar
12
Automotive Drives Novel IP Demands - Semiconductor Engineering
Mar
11
SoCs More Vulnerable to ESD at Lower Nodes - SemiWiki.com
Event Calendar
Spotlight
Webinar On Demand:
Noise Coupling Analysis for Advanced Mixed-Signal IC’s
ANSYS RedHawk 2014 Release Highlights
ANSYS RedHawk-CPA:
Accurate On-Chip Power Integrity and Reliability
