Resources

Ultra-Low-Power

Products Covered: PowerArtist, RedHawk, RTL Power Model (RPM)

Technical Papers and Presentations

Access to the following technical papers and presentations requires an Apache support account. Please login to your support account to access these files. If you do not have a support account, please either register for a support account or create a request. You will hear from an Apache representative within 48 hours.

  • System-Aware SoC Power, Noise and Reliability Sign-off
    This paper presents a a power noise and reliability methodology  for managing conflicting requirements of advanced process technology nodes — especially FinFET-based devices —  in globally competitive markets such as mobile, consumer and automotive electronic systems.
  • RTL Design-for-Power Methodology
    This paper presents a design-for-power methodology, beginning early in the design process at the Register Transfer Level (RTL) for maximum impact on power.
  • Low Power Design Analysis
    This paper describes the technology and methodology for analysis of designs utilizing power- gating switches for leakage control. It describes the requirements of verifying low power designs in different modes of operation, as well as in mixture of various states.
  • Electronic Power and Thermal Management
    This paper presents a set of tools and methodologies that help address the challenges of power and thermal management encountered in next-generation unmanned systems.
  • Ultra-Low-Power Methodology (Slides)
    This presentation demonstrates how  Apache enables successful design and delivery of low-power chips by offering a comprehensive flow that spans the entire design process.
  • RTL Power Analysis and Reduction (Slides)
    This presentation introduces PowerArtist, a complete RTL Design for Power  platform enabling micro-architectural trade-off decisions from beginning at RTL, “power debug”, analysis-driven RTL power reduction , and full-chip power regressions.
  • Power Integrity Verification and Signoff for Low Power Designs (Slides)
    This presentation covers RedHawk’s extensive capabilities for analyzing low power designs, while considering the complexities associated with various power saving features. It also highlights the low power debug capabilities of RedHawk Explorer and solutions for chip-package-system optimization.
  • PowerArtist (Slides)
    This presentation provides an overview of PowerArtist, a complete RTL Design- for-Power platform with fully-integrated advanced analysis and automatic reduction technologies; delivering 10% to 60% or more power savings.
  • Ultra-Low-Power Design Simulations – An RTL2Gate Approach (Slides)
    This presentation provides an overview of the industry's leading RTL Design-for-Power solutions - PowerArtist and industry-standard dynamic power sign-off platform - RedHawk,  along with RTL2Gate methodology on how these platforms can be used to meet complex and competing performance-power-price targets.
  • Ultra-Low-Power Design and Simulation Methodology: An RTL2Gate Approach (Webcast)
    This webcast will discuss PowerArtist, the industry's leading RTL Design-for-Power solution, and RedHawk, the industry-standard dynamic power sign-off platform, along with an RTL2Gate methodology for how these platforms can be used to meet complex and competing performance-power-price targets.

Contributed Articles

Conference Papers

Webinars and Videos

  • SoC Power Budgeting Using RTL Power Models
    This Educast will provide useful information regarding how PowerArtist Calibrator and Estimator (PACE) and RTL Power Models (RPM) can improve the accuracy of your RTL power estimation prior to the availability of physical implementation and manage power delivery network integrity early in the process for cost-effective IC and package design decisions.

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Power Integrity and Sign-Off

Products Covered: RedHawk, Totem

Technical Papers and Presentations

Access to the following technical papers and presentations requires an Apache support account. Please login to your support account to access these files. If you do not have a support account, please either register for a support account or create a request. You will hear from an Apache representative within 48 hours.

  • System-Aware SoC Power, Noise and Reliability Sign-off
    This paper presents a a power noise and reliability methodology  for managing conflicting requirements of advanced process technology nodes — especially FinFET-based devices —  in globally competitive markets such as mobile, consumer and automotive electronic systems.
  • Low Power Design Analysis
    This paper describes the technology and methodology for analysis of designs utilizing power-gating switches for leakage control. It describes the requirements of verifying low power designs in different modes of operation, as well as in mixture of various states.
  • Excel2IR Early Design Analysis and Power Grid Prototyping Utility
    This paper outlines an analysis methodology enabling early-stage design closure, with consideration for power grid parameter checks, such as required number and location of pads and power gates, power grid metal density used vs. reliability, and IR-drop targets.
  • Technologies for Power, Signal, Thermal, and EMI Sign-off
    This paper discusses the challenges associated with designing smaller, faster, and lower cost products. It provides an overview of Apache's power and noise solutions and how these products enable comprehensive chip-package-system convergence flow across multiple design disciplines.
  • Power and Noise Integrity for Analog/Mixed-Signal Designs
    This paper describes the need for power noise integrity solution for analog / mixed-signal designs and the benefits of the Totem platform, its usage model in a design flow, and results from simulation and correlation measurements.
  • Electronic Power and Thermal Management
    This paper presents a set of tools and methodologies that help address the challenges of power and thermal management encountered in next-generation unmanned systems.
  • Power Integrity Verification and Signoff for Low Power Designs (Slides)
    This presentation covers RedHawk’s extensive capabilities for analyzing low power designs, while considering the complexities associated with various power saving features. It also highlights the low power debug capabilities of RedHawk Explorer and solutions for chip-package-system optimization.
  • IP Integration and SoC Sign-off for Power, Noise and Reliability (Slides)
    This presentation demonstrates how Apache's IP Integration methodology enables successful integration of IPs on highly integrated mixed-signal SoCs by considering the power noise impact of sensitive analog circuitry with high-speed digital logic on the same piece of silicon
  • RedHawk™ - SoC Power Integrity and Sign-off for 28-nm Designs (Slides)
    This presentation discusses how RedHawk enables designers to explore and identify physical design weaknesses, automatically repair the source of supply noise, analyze the impact of dynamic voltage drop on timing and jitter, verify power and signal EM, and provide a model of the chip's power delivery network for system-level analysis.
  • Totem™ - Analog/Mixed-Signal Power Noise and Reliability (Slides)
    This presentation demonstrates how Totem addresses the challenges associated with global coupling of power/ground noise, substrate noise, and package/PCB capacitive and inductive noise for memory components, high-speed I/Os and analog circuit designs. It also discusses Totem’s ability to create a protected model representing accurate power profile of the IP for mixed-signal design verification.
  • RedHawk-3DX (Slides)
    This presentation provides an overview of RedHawk-3DX, the fourth generation full-chip power integrity and sign-off solution. It is re-architected to meet the accuracy and capacity demands of sub-20nm process technology and enables the simulation of multi-die / 3D-IC designs.
  • Totem (Slides)
    This presentation provides an overview of Totem, a full-chip, layout-based power and noise platform for analog and mixed-signal designs. It addresses the challenges associated with global couplings of power / ground noise, substrate noise, and package / PCB capacitive and inductive noise for memory components (Flash and DRAM), high-speed I/Os (HDMI and DDR), and analog circuits (power management ICs).
  • RedHawk-3DX: Fourth Generation Power Sign-off Solution Architected for 3D-IC Designs (Webcast)
    This webcast focuses on Apache's latest generation of the RedHawk platform - RedHawk-3DX - with direct support for multi-die simulation, including a brand new multi-pane, multi-canvas graphical user interface, its hierarchical dynamic simulation capabilities, new logic and activity propagation engines, and the ability to model and simulate LDOs.

Contributed Articles

Conference Papers

Webinars, Videos and Technical Briefs

  • SoC Power Integrity Challenges
    This educast covers, challenges in IC power integrity and low-power sign-off, simulation requirements for dynamic power noise on ICs using system-aware chip simulations, and simulation requirements for system co-design using chip-aware system simulations
  • RedHawk-3DX: Dynamic Power Sign-Off
    This webcast introduces RedHawk-3DX,  a fourth generation full-chip power integrity and sign-off solution re-architected to meet the accuracy and capacity demands of sub-20nm process technology and enables the simulation of multi-die / 3D-IC designs
  • Power and Reliability Sign-off
    This video presents on power and reliability sign-off using RedHawk and Totem in GlobalFoundries advanced 28nm low-power process
  • Power Issues Ahead
    This video talks about growing concerns over electrostatic discharge, electromigration, the impact of stacked die, and the need for power and thermal models.

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Chip-Package-System

Products Covered: RedHawk, Chip Power Model (CPM), Sentinel-PSI, Sentinel-SSO, Sentinel- TI

Technical Papers and Presentations

Access to the following technical papers and presentations requires an Apache support account. Please login to your support account to access these files. If you do not have a support account, please either register for a support account or create a request. You will hear from an Apache representative within 48 hours.

  • System-Aware SoC Power, Noise and Reliability Sign-off
    This paper presents a a power noise and reliability methodology  for managing conflicting requirements of advanced process technology nodes — especially FinFET-based devices —  in globally competitive markets such as mobile, consumer and automotive electronic systems.
  • ANSYS and Apache Technologies for an Integrated Chip-Package-System Flow
    This paper presents solutions for effectively managing design specifications (performance) and margins (price). It discusses solutions based on accurate and predictive simulation software from ANSYS and Apache that offers electronics designers a simulation-driven chip–package–system convergence methodology.
  • Technologies for Power, Signal, Thermal, and EMI Sign-off
    This paper discusses the challenges associated with designing smaller, faster, and lower cost products. It provides an overview of Apache's power and noise solutions and how these products enable comprehensive chip-package-system convergence flow across multiple design disciplines.
  • Electronic Power and Thermal Management
    This paper presents a set of tools and methodologies that help address the challenges of power and thermal management encountered in next-generation unmanned systems.
  • Simultaneous SI and PI Analysis for High Speed I/O Designs for Mobile Applications (Slides)
    This presentation provides an overview of a simulation methodology that simultaneously includes the switching impact of an entire bank of IO cells along with the associated IO ring PDN parasitics, the package and PCB parasitics including the coupling between power and signal nets, and the parasitics of the termination logic.
  • Chip Power Model: Next Generation Power Modeling Capabilities (Slides)
    This presentation discusses the Chip Power Model (CPM) technology, along with examples of how it is used for chip-package-system convergence. The newest functionality is presented with details on how it can provide greater verification and sign- off coverage, as well as resonance frequency aware CPM and chip-level probing in a chip-package-system simulation.
  • CPM -repeat_current Update (Slides)
    Describes the repeat_current functionality in CPM generation flow that enables long simulation by intelligently avoiding artificial di/dt effects during the current waveform repetition
  • Customizing User Configurable CPM (Slides)
    Explains the user configurable mode for CPM and how it can potentially be used to generate long duration CPM with various user-defined states.
  • Low-Power Design Closure with Chip-Package-System (Slides)
    This presentation provides an overview of 'system-aware' chip design and 'chip-aware' system design methodologies and how they address complex power and signal integrity, thermal, and electromagnetic interference (EMI) design requirements.
  • Sentinel-PSI (Slides)
    This presentation provides an overview of Sentinel-PSI, a 3D full-wave electromagnetic solver for power and signal integrity analysis of package and PCBs, with the ability to perform DC, AC, and transient simulations from a single environment.
  • Sentinel-SSO (Slides)
    This presentation provides an overview of Sentinel-SSO, a high-capacity I/O sub-system timing and noise analysis solution targeted for IC and package SI designers.
  • CPS Reference Flow and DesignCon 2011 Recap (Slides)
    Describes the CPS Reference flow covering guidelines, validation and training testcase. Also includes recap of CPS methodologies presented in DesignCon 2011 Workshop.

Contributed Articles

Conference Papers

Webinars and Videos

  • Power Issues Ahead
    This video talks about growing concerns over electrostatic discharge, electromigration, the impact of stacked die, and the need for power and thermal models.

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Advanced Reliability

Products Covered: RedHawk, Totem, PathFinder, Sentinel

Technical Papers and Presentations

Access to the following technical papers and presentations requires an Apache support account. Please login to your support account to access these files. If you do not have a support account, please either register for a support account or create a request. You will hear from an Apache representative within 48 hours.

  • System-Aware SoC Power, Noise and Reliability Sign-off
    This paper presents a a power noise and reliability methodology  for managing conflicting requirements of advanced process technology nodes — especially FinFET-based devices —  in globally competitive markets such as mobile, consumer and automotive electronic systems.
  • Power and Signal Line Electromigration Reliability Validation Challenges
    This paper describes EM integrity analysis for power and signal lines. It outlines the various process and design trends that are increasing the likelihood of EM induced failures and looks at conventional verification techniques for EM integrity and contrasts those with what is required for advanced process nodes.
  • PathFinder™: Solution for Full-chip IC ESD Integrity
    This paper describes how PathFinder helps designers meet ESD guidelines and identify “weak” areas of the design most vulnerable to ESD failures. It also demonstrates how PathFinder can be used for early prototyping and design exploration, especially when clamp cells are inserted inside the core region of the chip.
  • Technologies for Power, Signal, Thermal, and EMI Sign-off
    This paper discusses the challenges associated with designing smaller, faster, and lower cost products. It provides an overview of Apache's power and noise solutions and how these products enable comprehensive chip-package-system convergence flow across multiple design disciplines.
  • Electronic Power and Thermal Management
    This paper presents a set of tools and methodologies that help address the challenges of power and thermal management encountered in next-generation unmanned systems.
  • PathFinder™: Full-chip ESD Integrity and Macro-level Dynamic ESD (Slides)
    This presentation introduces PathFinder, the industry's first comprehensive layout-based electrostatic discharge integrity solution providing integrated modeling, extraction, and simulation capabilities that enable an entire IC analysis highlighting susceptible areas for ESD-induced failures.
  • ESD Integrity and Verification using PathFinder (Slides)
    This presentation describes ESD verification methodology at the full-chip and IP levels from early stage to sign off using PathFinder, the industry’s first ESD physical integrity solution. The presentation includes discussions on static rule based resistance checks and current density checks.
  • Reliability Analysis and Modeling for SoC and Custom Designs (Slides)
    This presentation describes EM analysis methodology of digital (SoC/ASIC) and custom/analog (IPs/macro) designs using Apache’s RedHawk and Totem platforms, a comprehensive analysis framework for accurate power and signal EM verification. The presentation will include discussions on advanced process and foundry EM rules, as well as self-heat analysis.
  • ESD Dynamic Methodology for Diagnosis and Predictive Simulation of HBM/CDM Events (Slides)
    This presentation discusses a comprehensive ESD dynamic methodology for failure diagnosis and predictive simulation with real HBM and CDM application examples. The methodology focuses on dynamic analysis including modeling of die-level metal grid, substrate grid and well diode, package effective capacitance, and pogo pin.
  • Reliability Analysis for 28/20nm (Slides)
    This presentation provides an overview of the evolution of reliability challenges for advanced technology nodes, along with the methodology for how to address these issues using Apache's comprehensive reliability modeling and simulation solutions for power and signal EM, full-chip ESD and thermal-stress integrity.

Contributed Articles

Conference Papers

Webinars and Videos

  • Design for Reliability - An IC Perspective
    This webcast discusses the various reliability phenomena that affect the design of advanced ICs and electronic sub-systems, as well as the various technology drivers and multi- physics simulation requirements for IC reliability analysis.
  • Power and Reliability Sign-off
    This video presents on power and reliability sign-off using RedHawk and Totem in GlobalFoundries advanced 28nm low-power process

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