RedHawk

 

RedHawk is the industry-standard dynamic power integrity solution from Apache with the capacity to handle designs with over billion gates, while maintaining sign-off accuracy. It analyzes the effects of simultaneous switching noise (core, memory, I/O), decoupling capacitance (intentional and intrinsic), on-chip and off-chip (package) inductance. RedHawk enables power methodologies from RTL to Gates, across Chip, Package and System, and supports the emerging 3D-IC / multi-die initiatives.

RedHawk allows designers to explore and identify physical design weaknesses (RHE), automatically repair supply noise source (FAO), analyze the impact of dynamic voltage drop on timing and jitter (PSI), verify power and signal EM (SEM), validate ESD protection robustness (PathFinder™), provide a power delivery network model profile for system-level analysis (CPM™), and allow modeling, simulation and debug of 3D-IC designs (MDO).

RedHawk (ALP) performs rush-current and ramp-up analysis, multi-mode verification, and intelligent switch optimization for ultra-low-power design techniques including multiple voltage islands, MTCMOS (power-gating), VTCMOS (substrate back-biasing), switched memories, and on-chip LDO (low drop-out) voltage regulators. RedHawk enables designers to meet the power budget, power delivery integrity, and power-induced noise immunity targets for their IC.

The fourth generation full-chip power sign-off solution targeted at sub-20 nanometer process and 3D-IC designs.

A full-chip and block-level dynamic power integrity solution for analysis and optimization of advanced low power designs.

A full-chip clock network integrity (jitter) and critical path timing signoff solution for high-performance nanometer designs.

A full-chip signal EM solution with accurate and detailed Average, RMS, and peak EM violation analysis.

A compact and SPICE-accurate model of the full-chip power delivery network behavior.

The industry's first comprehensive layout-based electro-static discharge (ESD) integrity solution.

Die modeling of the noise source, 3D full-wave electromagnetic simulation, and tools to pinpoint the origin of noise within the chip.