- PowerArtistRTL Power Reduction, Analysis, Debug, and RPM Generation
- RedHawkSoC Dynamic Power, Advanced Low Power, Reliability, and Chip-Package Co-design
- TotemAnalog/Mixed-Signal Dynamic Power, Substrate Noise, EM, and ESD
- SentinelChip-Package-System Power/Signal Integrity, IO-SSO, Thermal, and EMI
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- ResourcesTechnical Papers and Presentations, Contributed Articles and Conference Papers, Webinars and Videos
Apache Design's RTL Power Model Technology Honored with DesignCon 2012 Award
ANSYS Subsidiary Earns DesignVision Award for Innovative Electronics Software
PITTSBURGH – February 7, 2012 – A technology from Apache Design, Inc. — an ANSYS (NASDAQ: ANSS) subsidiary — has earned a prestigious award celebrating innovative electronics tools that simplify customer design processes. RTL Power Model (RPM™) won DesignCon 2012’s DesignVision Award in the System Modeling and Simulation Tools category. Launched in late 2011, RPM technology enables organizations to optimize a wide range of power-sensitive applications, such as ultra-low-power electronics. The product helps ensure that power-related decisions can be made with confidence early in the design flow by bridging the power gap from register-transfer-language (RTL) design to physical implementation.
This is the second DesignVision Award for Apache; its first was for PowerArtist™ technology in 2009.
“It is a privilege for Apache to be recognized with this award for our RPM technology, which optimizes a wide range of power-sensitive applications including ultra-low-power electronics,” said Dr. Andrew Yang, president of Apache and vice president and general manager of ANSYS. “This win underscores ANSYS’ and Apache’s deep commitment to consistently providing best-in-class products to our customers and the IC design industry.”
DesignVision award winners were selected based on three criteria: how well the product met the market’s vision and offered unique insight into customer needs; the originality of the solution and if it offered a new approach to meeting market needs; and the quality of the implementation and how well it fits the market requirements. RPM accurately predicts integrated circuit (IC) power behavior at the RTL level with consideration for how the design is physically implemented. As a result, the technology helps to enable chip power delivery network (PDN) and IC package design decisions early in the design process, as well as to ensure chip power integrity sign-off for sub-28nm ICs.
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February 7th, 2012