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ANSYS and Subsidiary Apache Design Selected for TSMC Reference Flows
Engineering Simulation Solutions Support TSMC’s 20nm and CoWoS™ Reference Flows
PITTSBURGH – October 15, 2012 – To meet market demands for low-power mobile, high-performance computing and consumer and automotive electronics, ANSYS (NASDAQ: ANSS) and subsidiary Apache announce that their simulation tools have been selected for TSMC’s 20-nanometer (20nm) Reference Flow and CoWoSTM (Chip on Wafer on Substrate) Reference Flow to meet power, noise and reliability requirements for ensuring timely and successful tape-out results.
As part of the TSMC 20nm Reference Flow, Apache made needed enhancements in its RedHawk™ tool to provide IR-drop and electromigration (EM) analysis based on 20nm process requirements such as current direction and power grid rule of DC EM.
TSMC’s CoWoS™ Reference Flow spans a suite of tools from ANSYS and Apache to manage thermal impact on 3D-IC structures, such as thermal run-away, stress and thermal-induced electromigration. RedHawk, Totem, Chip Thermal Model (CTM™) and Sentinel™-TI, along with ANSYS® SIwave™ and ANSYS Icepak®, provide complete system-level thermal analysis with consideration for chip behavior across CoWoS™ designs. Another key advantage of 3D-IC packaging is the support for Wide-I/O architecture, which enables the design of products with lower power and higher bandwidth data communication. The CoWoS™ Reference Flow includes Sentinel™-SSO interposer-based I/O jitter and timing simulation with package and board models extracted from SIwave, providing designers with accurate and early visibility of their chip’s performance.
“ANSYS and Apache solutions address power, noise and reliability challenges for the most advanced TSMC process nodes and emerging design technologies,” said Andrew Yang, president of Apache. “Our continued collaboration with TSMC enables us to provide optimized tools and methodologies for 20nm and CoWoS™ designs.”
“Using ANSYS and Apache solutions, customers will have the ability to produce more robust designs and quickly deliver their next-generation products to the marketplace with TSMC’s 20nm and CoWoS™ technologies,” said Suk Lee, TSMC senior director, design infrastructure marketing division.
To learn more about the broad portfolio of engineering simulation product offerings, visit ANSYS and Apache exhibiting at the TSMC Open Innovation Platform® Ecosystem Forum October 16 in San Jose, Calif. Apache will present “Verification of Power, Signal and Reliability Integrity for 3D-IC/Silicon Interposer Designs” during the EDA technical track.
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