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Totem-MMX

Totem-MMX is a transistor-level power/ground noise analysis and verification solution addressing static and dynamic power integrity needs from early stage in the design to sign-off validation. It addresses the verification of IPs designed using full-custom or semi-custom techniques for both analog and mixed-signal designs. Totem enables designers to verify power grid connection problems, identify high voltage drop causing mechanisms, and isolate electro-migration bottlenecks.

Capability Highlights

• Full-chip capacity with spice-level accuracy
• Transient power-ground noise and electro-migration analysis
• Built-in extraction and simulation engine for fast incremental and “what-if” validation
• Concurrent analysis of noise propagation through power delivery network, substrate network, and package/PCB parasitics
• Layout-driven analysis integrated with existing analog design environment
• Model generation capability for hierarchical full-chip and system-level simulation

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Power Noise Impact on Analog/Mixed-Signal Designs

With increasing frequency requirements on custom IPs, there is a need to use aggressive design styles from placing transistors closer together, switching them faster, and eliminating margins that become too expensive to maintain. This results in increasing switching current requirements, both temporally and spatially, and thereby injecting noise into the power and ground network, as well as the substrate.

Dynamic power and ground noise can affect reliable operation of circuits in several ways including hold-time/setup-time violations, “state-upset” in memory cells, delay push-outs in high-performance I/Os, etc. In order to address the issues associated with power noise on analog / mixed-signal designs, a new methodology and tools that delivers full-chip capacity, spice-level accuracy, integrated layout-driven flow, and the ability to generate accurate and high performance IP models for SoC analysis are needed.

Existing spice and fast-spice based solutions do not deliver the capacity and performance required to handle the complexities of power/ground RLC network with the transistor-level netlist. It is a single point tool solution that requires separate extraction engine and manual interaction to generate a netlist for simulation. In addition, it does not support incremental ‘what-if’ analysis without making layout changes, and does not support a hierarchical design methodology.

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Accuracy and Capacity

Totem-MMX incorporates transistor-level modeling with voltage de-rated switching current techniques, and spice-accurate decoupling capacitance extraction for highly accurate power noise analysis. It pre-characterizes the circuit using the Spice netlist, device models, and input vector set, and simulated with industry standard Spice simulators. The characterization process captures switching current waveforms for all switching transistors as a function of voltage for various operating conditions, as well as their intentional and intrinsic capacitance. It also considers the impact of package and board RLC through the support of broadband S-parameter package and PCB models.

Totem-MMX delivers the capacity required for standalone DRAM, Flash, and CMOS image sensors, as well as embedded memory macros. It leverages RedHawk-NX’s MPR (Mesh Pattern Recognition) extraction technology and multi-core simulation engine to handle designs of hundreds of millions of transistors.

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Layout-based Debugging Environment

Totem-MMX offers advanced viewing, debugging, and fixing capabilities to effectively analyze and optimize full-custom designs. Its layout-driven interface is integrated with existing analog design environments and supports cross-probing of power noise violations with the industry standard layout schematic tools and interactively analyze the fixes made in the design.

The powerful ‘what-if’ capability within Totem allows users to quickly verify a fix before committing to the layout. Fixes such as addition or removal of metal or via can be verified using incremental extraction and re-analysis to ensure that the proposed change does indeed fix the violation.

In addition, Totem debug environment shares its capabilities with the RedHawk SoC platform and therefore violations that are seen at the IP level using Totem can also be viewed and cross-probed at the SoC level using RedHawk. This gives SoC designers a unified platform for IP and SoC co-analysis and validation.

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IP Creation and SoC-level Analysis

Totem-MMX provides the capability to analyze and validate power noise issues at the IP level and generate a model of that IP that can be used in SoC or top-level power noise analysis. Totem incorporates top-level connectivity and noise coupling scenario for its block/IP-level analysis. Once validated, a detailed model capturing layout and circuit behavior of the IP is generated.

Totem IP model captures different operating states of the block such as “read”, “write”, etc. with its associated current and other parameters. It also enables designers to embed constraints such as maximum voltage drop allowance on transistors or a metal layer in the model for top-level verification.

To support multi-company IP integration, Totem provides various levels of IP encryption to protect the intellectual property of the circuitry. It delivers an optimized model for quick top-level analysis, while preserving the overall integrity and without compromising its accuracy.

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Power and Signal Reliability Analysis

Totem-MMX provides a single platform for power line and signal interconnect electro-migration (EM) analyses. Power EM is performed as part of static and/or dynamic analysis. Signal EM is performed in a separate run and checks for average, RMS, and peak current densities in all signal wires and vias.

Totem’s signal EM analysis flow includes pre-characterization of the signal nets to model average, RMS, and peak currents on the signal nets. These current values are compared against the specific limits defined in the technology file. The EM limits can be specified as a dependent on physical parameters such as width or length of the wire, or it can be specified as a polynomial dependent on width or length to support advanced process nodes. Based on the EM percentages calculated for each segment, the Totem GUI can display the design on net by net basis for easy debug.

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Integrated Power Noise Integrity Solution for Analog/Mixed-Signal Designs

Totem-MMX is a comprehensive solution that incorporates transistor-level noise injection, parastics extraction, package modeling, dynamic analysis, and design debug in a single-flow environment to enable analog/mixed-signal designers to mitigate design failure risks and reduce the product cost.

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