PathFinder

 

PathFinder is the industry’s first comprehensive layout-based electro-static discharge (ESD) integrity solution targeted to address the increasing reliability challenges faced by nanometer designs. PathFinder’s integrated modeling, extraction, and simulation capabilities enables automated and exhaustive analysis of the entire IC, highlighting weaknesses in the design that can be susceptible to failure caused by an ESD event. It also provides innovative transistor-level dynamic ESD capabilities for validation of I/O, analog, and mixed-signal macro designs. From early prototyping to sign-off, designers can use PathFinder to identify the most vulnerable area of the design, meet ESD guidelines, and improve product yield.

Key Benefits:

  • Capacity and performance for static ESD verification of 100 million+ instances, including power/ground RLC, substrate RC, and package parasitic, with overnight turnaround time
  • Comprehensive coverage with full-chip analysis of ESD events such as Human Body Model (HBM), Machine Model (MM), and Charged Device Model (CDM)
  • SPICE like accuracy for dynamic ESD simulation of 100’s of thousands of transistors block, including clamping devices and their snap-back characteristics
  • Layout-based GUI environment with feature rich debugging capabilities such as cross probing, ‘what-if’ analysis, and device failure rankings

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Key Functionalities:

Full-chip ESD prototyping and sign-off

  • Placement and connectivity validation
  • Resistance verification
  • Current density check

Block-level ESD dynamic simulation

  • ESD device modeling (e.g. clamp cells)
  • SPICE accurate analysis and optimization

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What is ESD?

Electro-static discharge is defined as a ‘transfer of energy between two bodies at different electrostatic potentials, either through contact or via an iodized ambient discharge (spark)’. It results in a current flow in the range of tens of Amperes over a very short duration time, typically 10 to 150 nano-seconds. As a result, the component that the charge passes through gets “zapped” with current and voltage greater than what it was designed for, thus leading to damaged parts.


Figure 1: ESD phenomenon


To help prevent ESD related failures, designers are placing protection circuits in key locations of the IC, especially at the I/O and power/ground pads. In addition, the increasing number of independent power/ground supplies on an IC is requiring placement of protection circuits inside the chip (core region). These protection circuits or clamp cells are placed to provide robust and efficient discharge path between any one pin/pad/bump to another, diverting the high current and preventing damage to the sensitive transistors.


Figure 2: ESD protection inside of a device

There are several ways that the charge can be transferred to the IC. It can come from an outside source such as human interaction with the IC pins (HBM) or from machine handling of the IC assembly (MM). These events can break down the junctions in the transistor, as well as the wires and vias. The zap can also come from within the IC as the built up charge leaves through the package (CDM). This scenario can cause damage to the gate oxides of the transistor, such as gate oxide punch-through, which can be catastrophic.

Figure 3: Various ESD event model and associate discharge waveforms

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ESD Challenges

Electronic components have experienced ESD failures for many years. But more recently, 1) shrinking geometries, 2) higher levels of digital and analog integration with isolated and independent power/ground networks, 3) broader use of hand-held devices, and 4) advanced package designs with tighter pitch and complex shapes are exacerbating the impact of ESD. The protection circuits include a trigger point, a snap-back holding point, and a thermal breakdown point, which helps prevent pin voltage from exceeding the oxide breakdown voltage.

Figure 4: Snap-back characteristics of a clamp cell and shrinking of the ESD protection window

However, moving to smaller process nodes imposes constraints on the design of the ESD circuits and their snap-back profile, as the oxide breakdown voltage continues to shift left while the thermal failure limits continue to move down, thus compressing the region in which the clamp circuit can provide protection to the chip.

Also the cost associated with ESD induced failure can be significant, whether from insufficient protection resulting in low yield, or from excessive or ineffective protection resulting wasted silicon real estate. While process migration shrinks the size of the logic circuits, the size of the ESD protection circuit do not scale accordingly. Thus the challenge for the designer is to tradeoff sufficient ESD protection versus lowest possible silicon real estate cost.

Traditional approach to ESD verification includes following engineering guidelines for layout, performing plot checking, and running design rule (DRC) checks. But these approaches cannot ensure that the overall resistance and current density of the ESD paths is below the threshold limit. As the complexity of the design and the number of power/ground nets increases, traditional methods cannot exhaustively identify devices or wires that may potentially fail during a specific ESD event before tape-out.

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PathFinder: ESD Integrity Solution

PathFinder, a layout and circuit verification technology addresses the limitations in today’s design validation process and methodologies. Using block level static and dynamic techniques and full-chip level static techniques, PathFinder can verify that the design meets ESD guidelines, and identify weak areas of the design in layout or circuit. It can report if the current density exceeds the limits for wires, vias, and clamps and provide a GUI environment for debugging the violating paths. In addition, PathFinder can perform early prototyping and design exploration, helping designers make area and metal routing tradeoffs.

Figure 5: PathFinder use flow

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Full-chip Static ESD Verification and Sign-off

The two goals of full-chip ESD verification and sign-off are 1) ensure that the connectivity between any two pins/pads/bumps meets the design guideline, and 2) predict the current density in all the wires and vias. PathFinder verifies the placement and connectivity of ESD cells for HBM, MM, and CDM, based on the layout information and design rules. It leverages the industry standard, high capacity extraction and simulation technologies in RedHawk and Totem to handle large SoC and custom designs. It computes the impedance in the discharge path through distributed power/ground and package mesh, as well as participating clamp cells.

HBM/MM Checks:

PathFinder verifies the effective resistance a) between any two pads/bumps traversing the network through a clamp cell, b) between pads/bumps to every connecting clamp cell, c) between multiple clamp cells; and d) between active devices and clamp cells for pass/fail check.

Figure 6: Effective resistance calculation for various scenarios

CDM Checks:

PathFinder estimates the effective resistance from the devices in the IC to the clamp cells that are inserted to provide a discharge path for the charge coming from these devices. It first calculates the “arc” resistance, which is the resistance on any one branch (e.g. Vdd to device or device to Vss). Then it calculates the loop resistance from the following connections: Vdd pin of the device to Vdd pin of the clamp cell, clamp cell resistance, and Vss pin of the clamp cell to Vss pin of the device.

Figure 7: PathFinder analysis flow for cell to clamp connectivity checks

Current Density Checks:

Increasing current flow through the metal layers of the discharging path can also cause electro-migration (EM) induced damages to interconnects. PathFinder provides current density check for all power/ground metals, I/O nets, and clamp devices. It can model the injection of current into any pad and perform an iterative DC analysis to identify pin-clamp-pin paths that are effective in conducting current. It then estimates the current density in all the wires connected to those pads. PathFinder highlights the wire/vias that fail the current density limits, allowing the designers to verify that the current flow during discharge event is within the established limits defined by technology or process guidelines.

Figure 8: Current density and electro-migration map showing location of zap and impact on EM

GUI Based Debugging:

To assist the designers in improving their design, PathFinder provides extensive analysis and debugging options, including reports, histograms, and graphical displays overlaid on the layout. “What-if” analysis with interactive clamp cell insertion and removal allows designers to verify their fixes from within the PathFinder simulation environment. Once the changes are confirmed to resolve the issues, a text based report (ECO) can be written out to guide the implementation of the changes in the final layout.

Figure 9: Different reporting and display options available in PathFinder

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IP Level Dynamic ESD Analysis and Optimization

Time-domain simulation of an ESD discharge event, especially for CDM mode, is required to identify parts of the circuit that are at risk and perform circuit level optimizations to address such issues. PathFinder can simulate transistor-level netlist such as I/Os, PLLs, and Serdes. It incorporates eSIM™, Apache’s proprietary transient non-linear simulator for ESD dynamic analysis. eSIM can handle negative resistance in snap-back devices without convergence issues that affect the traditional SPICE engines. Its dedicated matrix solver can handle large scale power/ground, substrate, and package mesh networks, including non-linear devices.

PathFinder also perform stress analysis across junction voltages of all transistors during the simulation, to help identify weak points in the design that can result in device failure due to ESD events such as CDM.

PathFinder leverages the Totem GUI and its rich usability including overlaying of the ESD transient simulation results onto the layout. Designers can simultaneously view the simulated netlist, analyzed layout, and various stress analysis results with the ability to rank the failures. It also provides cross-probing capability between the layout and the various results windows, making debugging and analysis considerably easier. PathFinder’s “what-if” analysis capabilities allow the designers to experiment with various fixes, including clamp cell insertion and removal,  before committing them to layout.

Figure 10: Multi-pane PathFinder GUI for IP level dynamic analysis

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