Sentinel-TI is a thermal simulation and mechanical stress integrity analysis platform for SoC and stacked-die/3D-IC designs. Through comprehensive modeling and simulation, Sentinel-TI enables engineers to accurately predict the thermal behavior of the chip and package, including its impact on chip-package reliability and stress.
|Chip-Package-System thermal co-analysis through power/thermal data interface|
Increasing design complexity and the use of stacked-die/3D IC increases the impact temperature has on power noise, reliability and performance. The temperature gradient on a chip can be two to five times greater when using fine-grain, temperature-dependent power density map versus a uniform on-chip power profile. Because the temperature gradient across a chip and the corresponding package depends on factors such as power, on-chip activity, location of memories, high-power cells, operating modes, etc., neglecting to take the temperature gradient of the package during analysis can impact the functional yield of an SoC design.
Chip-Package-System thermal co-analysis through power/thermal data interface
Sentinel-TI offers key capabilities for thermal simulation and mechanical stress integrity analysis of next-generation SoC and stacked-die/3D-IC designs:
- Comprehensive modeling for accuracy
- Prediction of the thermal behavior of chip and package
- Multi-activity chip thermal transient analysis
- Thermal resistance and reliability analysis of the package, including thermally induced stress and warpage
A methodology based on RedHawk/Totem, Icepak and Sentinel-TI enables chip-package-system power/thermal analysis and optimization.