- RedHawkSoC Dynamic Power, Advanced Low Power, Reliability, and Chip-Package Co-design
- PowerArtistRTL Power Reduction, Analysis, Debug, and RPM Generation
- TotemAnalog/Mixed-Signal Dynamic Power, Substrate Noise, EM, and ESD
- PathFinderESD Planning, Verification and Sign-off
- Sentinel-SSOI/O DDR Power Noise and Timing Analysis
- Sentinel-TIThermal Simulation and Mechanical Stress Integrity Analysis
- Supported Platforms
- ResourcesTechnical Papers, Presentations, Contributed Articles,Conference Papers, Webinars, Videos
ANSYS Sentinel-SSO delivers features that enable IC, package and system designers to analyze and optimize the timing and power/ground noise of parallel (DDR) I/O subsystems.
Integrated I/O-Aware SI & PI Analysis Integrated I/O-Aware SI & PI Analysis
A signal’s delay and output slew depend on the voltage being supplied to the I/O buffer, which, in turn, is dependent on PDN as well as the buffers’ current consumption. When power integrity (PI) and signal integrity (SI) are analyzed independently, the worst-case corner values are used to estimate the influence of one on the other. Using such a method can result in unnoticed inter-relation issues or overdesign. By analyzing both the parallel interface’s power and timing with nonlinear coupling, you can better ensure proper functioning signal channels.
Sentinel-SSO enables a full-I/O bank simulation along with all the associated on-chip, package and PCB parasitics for power-ground and signal net. It accurately predicts the impact of SI and PI effects on signal propagation and jitter for high-speed parallel (DDR) interfaces. The software creates proprietary models of the I/O ring (buffers, interconnects) to achieve full-I/O bank capacity while maintaining transistor-level accuracy.
Sentinel-SSO modeling overview
Accurate Macro Modeling Accurate Macro Modeling
Sentinel-SSO accurately models the nonlinear, physical nature of underlying circuits in a compact, SPICE-friendly format.
Chip I/O Model
Our tools create a chip I/O model (CIOM), a nonlinear behavioral model of the I/O buffers. These compact models accurately capture the electrical behavior of an I/O buffer, including degradation of its output signal in the presence of power/ground noise. Using these models enables full I/O bank simulation capacity while providing transistor-level accuracy.
Circuit details represented in chip I/O model (CIOM)
I/O Ring PDN Macro Model
Sentinel-SSO accurately models passive and parasitic effects from on-chip routing. It extracts both signal and power/ground supplies from the on-chip routing and produces a reduced-order model that behaves the same as the original network. These distributed RLC models with reduced orders-of-magnitude elements enable faster simulation throughput while maintaining full-detailed accuracy.
Extraction example of I/O ring macro modeling
Chip Signal Model
Combining I/O buffer models (CIOM) and I/O ring PDN macro-models accurately captures the electrical behavior of an I/O ring in a compact, SPICE-friendly, portable format. The combination is called a chip signal model (CSM). I/O DDR designers can provide a CSM to their package or PCB design counterparts, enabling I/O-aware package or PCB design and optimization.
On-Die PDN Debugging & Root-Cause Analysis
Using the power integrity explorer capability of Sentinel-SSO, designers can probe on-chip power and ground routing for weaknesses. You can compare the interconnectivity of the I/O, decap and power/ground bumps, individually or as a whole, using histograms to identify, isolate and fix routing issues that can adversely affect the circuit’s operation.
Sentinel-SSO power integrity explorer GUI
Integrated What-If Modeling & Analysis Integrated What-If Modeling & Analysis
Sentinel-SSO can read in the package layouts for integrated what-if modeling and analysis. Performing a quasi-static analysis generates RLCK models that can help separately identify ground bounce from the power network noise. The software can perform quiet-line analysis and track the voltage differences between nodes and ground supply network.
Sentinel-SSO what-if analysis with modification to package model
Using what-if capabilities, you can estimate how changes to the chip layout or the package layout affect SSO. For example, on-chip decap values can be changed to simulate the effects of larger or smaller Cdie; extra routing can be added to the chip to estimate grid connectivity improvements; package routing, decaps, stack-up dimensions and material properties can be changed to model their sensitivity on SSO.
Early SSO Analysis
Sentinel-SSO can perform I/O-SSO analysis early in the design cycle, before chip or package layouts are available. Designers can model the chip as pre-layout and specify the needed I/Os and decaps on the die.
For the package or PCB model, a designer can use Sentinel-SSO’s channel prototype modeling capability. This enables quick simulationsto help guide optimal package swlwction for the high-speed interface. I/O designer can experiment with I/O and decap configurations to determine the setup that best meets the interface’s SSO specifications.
Defining power specification for early prototyping with Sentinel-SSO