- PowerArtistRTL Power Reduction, Analysis, Debug, and RPM Generation
- RedHawkSoC Dynamic Power, Advanced Low Power, Reliability, and Chip-Package Co-design
- TotemAnalog/Mixed-Signal Dynamic Power, Substrate Noise, EM, and ESD
- SentinelChip-Package-System Power/Signal Integrity, IO-SSO, Thermal, and EMI
- Supported Platforms
- ResourcesTechnical Papers and Presentations, Contributed Articles and Conference Papers, Webinars and Videos
Chip Power Model (CPM) is a compact and SPICE-accurate model of the full-chip power delivery network. It contains spatial and temporal switching current profile, as well as parasitics of non-linear on-chip devices including decaps, loading capacitance, and power/ground coupling capacitance. CPM represents the entire die power delivery network with ports at the die level C4 bumps and/or pads. It accurately models the electrical response of the chip for a wide range of frequency, from DC to multi-GHz, thus enabling the analysis, diagnostics, and optimization of system-level power integrity designs.
As the de facto standard for die modeling, CPM leverages the full-chip time-domain and DC analysis technologies available through RedHawk™ and Totem™ platforms to create compact, yet highly accurate electrical representation of the chip in various operating modes. The latest evolution of CPM includes advanced modeling capabilities needed for a wide range of applications targeting chip-package-system analysis and optimizations.
Figure 1: System connectivity using CPM
- An accurate silicon correlated model representing actual die operating behavior
- A flexible and compact SPICE model for quick turn-around of chip-package-PCB system verification
- Optimization of package and PCB design from early design through sign-off stages
Applications for IC-aware System Verification
- Dynamic voltage noise budgeting at board and package level
- Global power delivery network (PDN) target impedance calculation and resonance prediction
- Package and board optimization from prototyping to sign-off
- System-in-Package (SiP) design analysis
- Models entire on-chip power delivery network including device level current (switching and leakage) and parasitic (diffusion, gate, signal, well) information
- Creates multiple port network with cross-coupling elements
- Distributed model of multiple power and ground domains
- Die response model over a wide frequency range, from DC to multi-GHz
- Represents various operating modes of the die
- Supports different types of system level analysis - AC, DC, transient and EMI
- Models resonance aware current excitation to verify worst case system behavior
- Models variable power transitions of the die (e.g., from low to high power modes) to verify system’s transient response
- User configurable customization for simulation of different operating modes without model recreation
- Creates ports at internal node locations to enable probing at transistor locations
Accuracy and Performance
Traditionally, the global power delivery network (PDN) is represented as a simplified model with a single current source, resistance, and capacitance network for the die, and lumped RLC parasitic elements for the package and the board.
Figure 2: High-level electrical model of chip-package-system using CPM
This simplified model of the die’s power delivery network can result in inaccurate global power analysis as die current can influence the voltage drop through the system and the resistive and capacitive components of the die can determine the resonance frequency and its amplitude. Thus an accurate representation of the die’s PDN is critical in determining the quality of the system power integrity.
CPM generates power/ground network model as current sources and R, L, and C parasitics. CPM takes the entire network, which contains several linear and non-linear elements, and provides a reduced view of effective Rdie and Cdie for different frequencies of operation.
Figure 3: Electrical model of CPM
It also provides switching current information from the active logic that varies over time and space, reflecting the real operation of the chip over a range of frequencies. By including all the different parasitics and elements of the die, CPM offers a true representation of the chip.
The accuracy of the CPM model can be determined through a self-consistency check. This check consists of comparing an analysis of full die and package with a simulation of reduced model using CPM and the package with a CPM. In a full die analysis, the entire die is simulated in RedHawk at the cell or transistor level with a detailed package SPICE netlist to derive the current and voltage at every bump location of the design. In the CPM run, the CPM SPICE model is used to represent the die. Both analyses give us similar results when comparing the total current demand, and the VDD/VSS bump voltages.
Figure 4: RedHawk analysis using detailed die model vs. SPICE simulation using CPM
This self-consistency check validates that CPM is accurate. CPM reduces very large chips with 100s of millions of nodes to a SPICE level model that is able to capture the current requirements and other complex effects that are seen on the die.
One of the key motivations for generating a CPM is to perform IC-aware system design. CPM delivers reduced order model that enables designers to run multiple iterations of system design analysis and optimization. SPICE-based simulation of the package with CPM model will run within minutes versus full-chip dynamic power analysis that can take hours to perform.
From Prototyping to Sign-off
CPM can be applied early in the design process to help direct the designers in package selection, pad placements, decap strategy, and impedance management. By having an accurate representation of the IC power deliver network (PDN), the designer can confidently make cost critical package/board design decisions to mitigate design failure risk and reduce overall system cost.
Figure 5: CPM-based analysis flow
As design moves through the process, CPM can be used to incrementally improve the system design to avoid any last minute surprises at the end of the design cycle.
Impedance Calculation and Resonance Prediction
To design a good package, the designer needs to ensure that the input impedance is below the target impedance, and that the resonance frequency does not overlap with the functional frequency of the chip.
Figure 6: Impedance profile based on varying capacitive components
CPM contains Cdie (die capacitance) which impacts the frequency of the resonance, and Rdie (die resistance) which impacts the amplitude of the resonance. By generating different CPM for varying capacitive components, the designer can observe its impact on impedance profile and make the well informed decisions that meet the design criteria.
Dynamic Voltage Noise Budgeting
The voltage drop distribution of the system is only as valid as the die model that is used for the system-level analysis. Using a simplified model of the die with triangular current profile can result in inaccurate view of the dynamic voltage drop distribution. By using CPM in the package/board analysis, designers are able to gain more accurate view of the location and magnitude of the dynamic voltage drop, as it considers the real operation of the chip.
Figure 7: Package voltage drop map with and without chip power information
By measuring the transient voltage waveforms at the different on-die bump locations, designers can identify noisy areas on the die and to understand where and how the power noise can be optimized.
Figure 8: Transient voltage waveform and current profile
CPM includes advanced modeling technologies that can be used for a wide range of applications targeting chip-package-system analysis and optimizations.
Probing Device Locations Inside the Chip
Users can create a CPM with ports at the transistor device location inside the chip. This allows the user to consider the drop through the on-die power delivery network in a fast system level simulation. The package or board designers can run experiments using the CPM to see the impact of their change at the bump location and deep inside the chip at critical device locations, as shown below.
Figure 9: Voltage drop measured at the bump vs. device
Advanced Excitation Modes
While frequency domain simulations are used to understand the various resonance points of the combined power delivery network, time domain simulations are also required to model the actual operation of the system and to measure the efficiency of the various decoupling elements. The resonance aware mode of CPM creates current signatures where most energy is around the chip-package-system resonance frequency, while maintaining the logic and timing properties of the circuit. This methodology mimics a low frequency power transient behavior by introducing a frequency that is modulated on top of the major clock frequencies, thus enabling the system verification for a worst case scenario and allowing for stress test of the system power delivery network.
The dynamic voltage drop must be validated during different on-die power transients. The variable power mode of CPM captures the power step up such as the impact of the chip transitions from reset to running mode, traffic to no traffic mode, and memory on to off mode. These power transients impact the entire VRM, board, package, and die system to varying degrees based on the duration and amplitude of the power step.
The user configurable CPM allows the package and board engineer to mix-and-match contribution from different regions (user specified) or functional blocks of the die, creating unique scenarios that reflect different operating states of the chip. It can be used to customize multiple individual system simulations, targeting specific operating models without regenerating the CPM for every single operation mode. Some applications for User Configurable CPM are (1) to predict near and far field radiation spectra where certain blocks in the chip can be turned off to study the impact of the block activity on the observed radiation and (2) to study the current contribution from different portions of the chip and their impact on voltage drop for power delivery analysis. This approach helps identify the source of noise by exploring different die activity scenarios and to understand the block level contribution to the overall system noise.
IC-aware Package and Board Analysis
Without an accurate model of the chip's power deliver network, engineers often times guard-band their package designs to protect against unknown power integrity issues. But this method can result in more complex package and/or more decaps on the board than necessary and ultimately higher cost system.
By using CPM, system designer gain access to accurate model of the IC PDN allowing them to analyze the impact of die-package LC resonance on the performance of global PDN and perform "IC-aware" voltage drop analysis in both time and frequency domain for package and PCB. CPM enables designers to perform better noise budgeting and optimize their package selection early in the design process to reduce cost and minimize design risk.