ANSYS PowerArtist enables RTL-to-GDS design for power methodology by providing early RTL power estimation and analysis-driven power reduction capabilities. RTL designers working on a variety of applications, from mobile to CPU to networking to automotive ICs, use PowerArtist to optimize designs throughout the development cycle.
|Watch this video to learn how PowerArtist, the RTL Design-for-Power platform, allows you to visualize, analyze and optimize power, and enables physical-aware power budgeting.|
Predict Power in Early Stages
Embedded PowerArtist Calibrator and Estimator (PACE) technology ensures that early RTL power estimates track the final gate-level power numbers. PACE supports a wide range of process technology nodes and design styles, so R&D teams can confidently make design trade-off decisions using early RTL power estimates. This shifts methodology away from time-consuming gate-level power analysis, a difficult-to-use process that is often done late in the design cycle.
PowerArtist RTL power flow vs. gate-level power flow
Eliminate Power Waste to Meet Aggressive Power Targets
PowerArtist helps you to identify areas of power waste within your design, then provides guidance on how to eliminate them. As dynamic power management becomes a significant issue, RTL analysis must consider clock network, datapath and memory architectures for ways to reduce power consumption and meet power budget targets. PowerArtist’s feature-rich GUI incorporates powerful visualization and debug capabilities, enabling RTL designers to identify and eliminate power bugs.
Track Power and Related Metrics
PowerArtist offers an open-access database- (OADB) compatible API interface to report design properties and power-related metrics. Design teams use it to generate custom reports and track various metrics through their RTL design process. PowerArtists’s rapid turn-around time, RTL power estimation accuracy and rich TCL capability set enable power regression.
Complete RTL-to-GDS Power Methodology for Increased Sign-Off Coverage
As RTL to GDS sign-off time shrinks, design teams find it critical to leverage information across design phases to avoid overdesign or underdesign. PowerArtists’ RTL Power Model (RPM) technology enables you to create a model that contains relevant information from your RTL power simulations. The design team can incorporate use this model with ANSYS RedHawk ― our SoC power noise and reliability sign-off platform ― to perform early chip-package power grid prototyping or dynamic power noise sign-off. RTL to GDS methodology can increase analysis coverage and provide greater confidence prior to tape-out for increasingly complex ICs.
Ultra-low-power methodology using ANSYS PowerArtist
PowerArtist is the RTL power solution of choice for all leading low-power semiconductor companies in the world.