- PowerArtistRTL Power Reduction, Analysis, Debug, and RPM Generation
- RedHawkSoC Dynamic Power, Advanced Low Power, Reliability, and Chip-Package Co-design
- TotemAnalog/Mixed-Signal Dynamic Power, Substrate Noise, EM, and ESD
- SentinelChip-Package-System Power/Signal Integrity, IO-SSO, Thermal, and EMI
- Supported Platforms
- ResourcesTechnical Papers and Presentations, Contributed Articles and Conference Papers, Webinars and Videos
CHIP-PACKAGE-SYSTEM (CPS) SOLUTIONS
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As technologies evolve to meet the demands of higher performance, smaller size and lower cost, there are several challenges in the design of chips, packages and boards that require an integrated analysis and verification methodology. Challenges of power drawn by the chip and from power delivery through the board, package, and on-die power delivery network (PDN) are no longer just the chip designers’ problem, but also require all the parties involved in the design of the system to comprehend and address from the beginning of the design process.
Existing tool sets address only parts of the problem. For example, frequency domain analysis tools employing fast electromagnetic field solvers address the mid- and low-frequency PDN system noise, while the time domain analysis tools solve the high-frequency noise that results from the switching of devices on the chip. For I/O signal integrity analysis, most methods compromise accuracy and completeness for a reasonable runtime. As a result, either the entire I/O bank is not considered in the simulation or the signal/power ground network coupling is ignored, impacting the quality of the results that are critical in determining whether the chip-to-chip transmission will happen according to the specifications.
Chip-Package-System Co-analysis Requirements
Addressing the many aspects of Chip-Package-System co-analysis such as signal integrity, power integrity, and electromagnetic interference require an integrated solutions with the following key capabilities.
- Comprehensive model of the chip(s)
- Accurate model of the package and board
- Co-simulation platform that can take chip, package, and board models appropriately to perform required simulations (frequency domain, DC, or transient)
Chip-aware Package/PCB Analysis
Chip-aware package/PCB analysis requires access to an accurate model of the die by the package/PCB designers. Chip Power Model (CPM™) from Apache Design Solutions models the entire power delivery network (PDN) for all the power and ground domains along with device current (switching and leakage) and parasitic (diffusion, gate, signal, well, etc.) information to create a SPICE-based model with ports created at the die level C4 bumps and/or pads. The model can accurately represent the electrical response of the chip for a wide frequency range, from DC to multi-GHz.
CPM enables package and board designers to perform package and board level AC, DC, time-domain and EMI/EMC simulations by factoring in the presence of the die(s), and allowing them to optimize their package and board designs with very quick turnaround times. Without CPM, package and board engineers have to analyze their designs using heuristic based models of the die and/or certain assumptions.
An accurate modeling of the die requires following technologies supported by Apache’s CPM.
- Capacity to handle an entire chip layout along with device information
- Extraction of the on-die PDN parasitic and coupling
- Inclusion of all device and other capacitances
- Reduction of large netlist (>100M nodes) into a behavioral model that can be interpreted and simulated by SPICE engines
The accuracy of the model is validated by comparing the simulation of the chip with its package model using RedHawk™ and the bump-level current and voltage waveforms of its equivalent CPM with the same package simulated in SPICE.
CPM provides both parasitic and activity information for the die allowing it to be used in various PDN verification. The availability of parasitic information enables impedance analysis of the system PDN, while the activity information enables DC and time-domain simulations. The activity on the chip can be generated using VCD and/or vectorless techniques to consider the resonance of the system, thus giving system PDN engineers with a model that can be used to stress their designs.
By integrating CPM with Sentinel™-PSI, package and PCB designers can perform chip-aware package and PCB power and signal integrity analysis. This enables designers to start their planning and design before a completed chip design is available and achieve system sign-off with higher quality and lower cost results.
Package/PCB-aware Chip Analysis
On-die voltage drop analysis is incomplete if the package and PCB geometries are not considered in the simulation. These not only cause increased parasitics, but also provide additional “redistribution” layers for the current flow. The board parasitic can impact the dynamic noise by as much as 20% of the total drop and depending on the package layout (L) and on-die switching (di/dt) signature, the drop across the package can be as much as 70% to 80% of the total drop.
The design, optimization, and verification of the chip PDN must be performed in conjunction with design and optimization of the package in which the chip will reside, and the PCB on which the packaged chip will be mounted. As most package structures have fragmented routing to accommodate multiple signal and power/ground nets in few package layers, 3D full-wave extraction technologies are required to accurately model these shapes and capture the fringing effects such as imperfect ground planes and boundary reflections. Sentinel-PSI leverages advanced meshing and multi-CPU solver technologies to rigorously solve Maxwell’s equations and generate accurate broadband models of the package and PCB. By including the package/PCB models into the chip simulation, designers can achieve higher quality results.
Supply Noise Impact on Chip and System Performance
Power supply noise not only affects the functionality and performance of the chip, but also impacts the way it interacts with its environment and other chips. Voltage degradation is the most common cause of parts not achieving volume shipments at higher speeds and the impact of dynamic power noise on high-speed memory interface signal transmission can have significant impact. Sentinel™-SSO is an I/O sub-system timing analysis solution that incorporates on-die, package, and board parasitics (signal and power), the current demand of the switching circuit, and the associated capacitances. For example, it takes the I/O ring layout of DDR interface, SPICE data of the netlists/models, and switching testbench, along with the package and PCB layout to create a unified simulation environment, capturing the impact of power grid noise and signal cross-talk on the propagation of the signal from a DDR interface to a memory chip.
Sentinel-SSO delivers accurate I/O sub-system timing analysis by considering the impact of simultaneous switching of the entire I/O bank on the I/O ring power supply modeled in full RLC details, and the broadband S-parameter based models of the package and PCB parasitic that include both power/ground and signal net parasitics by themselves, as well as their cross-coupling.
Another area of concern, especially for automotive and consumer applications, is the increasing impact of power/ground noise on the electromagnetic interference (EMI) signature of the system. The chip in the system acts as the generator of noise, which is then propagated to outside of the chips through their package and the board power and signal traces, and is radiated by the cabling. By understanding the chip noise signature, the designers can perform accurate near and far field simulations and fix the system to meet the EMI requirements prior to tape-out.
CPM provides early visibility of the EMI noise source so that the system designers can accurately predict their system EMI signature early in the design process. In addition, the chip designers can use RedHawk and Totem™ to better understand the frequency components of the on-die noise, the distribution of the noise over the chip, and the cause of the noise. This enables designers to implement chip-level fixes for addressing EMI failures instead of system-level fixes which can be costly.
Power noise and its associated challenges have to be addressed holistically in every step of the design process, from the product definition step to the final design sign-off stage by the respective owners. A comprehensive modeling, co-analysis, and optimization methodology ensures that the design objectives for power integrity, circuit performance, reliability and regulatory compliance are met.