Apache Announces RedHawk-LP, a Dynamic Power Integrity Solution for Low Power and Leakage Control Designs

MOUNTAIN VIEW, Calif. – May 15, 2006 - Apache Design Solutions, the technology leader in physical power integrity solutions for system-on-chip (SoC) designs, today announced RedHawk-LP, a dynamic power integrity solution for analysis and optimization of low power and leakage control designs. RedHawk-LP provides the most accurate and complete power solutions for designs utilizing various low power and leakage management techniques, including power-gating with full-chip ramp-up analysis and switch optimization, and multiple-Vdd/Vss cells with multiple voltage domains.

RedHawk-LP expands Apache’s silicon-proven full-chip dynamic power integrity product portfolio by delivering the most advanced power analysis and design optimization solution for low power SoCs.


Leakage: A Dominant Source of Overall Power
At 90nm and below, leakage will start to dominate the chips overall power. Engineers are employing techniques such as power-gating or multi-threshold-CMOS (MTCMOS) switches to control the amount of leakage in their designs. RedHawk-LP’s Spice-accurate MTCMOS switch modeling, full-chip capacity and performance, and true-transient simulation engine enable designers to accurately analyze the chip’s non-linear behavior during ramp-up (sleep to active), including how the current surge during ramp-up impacts the timing of surrounding logic. RedHawk-LP supports mixed-mode analysis where designers can analyze how simultaneous “ON,” “OFF,” and “power-up” states impact the chip’s overall power and timing.

To guide the designers in identifying potential design issues, RedHawk-LP provides various visualization tools such as current profile, Vdd/Vss waveforms, and full-chip movie playback. By using RedHawk-LP’s movie mode, designers are able to view the instance-based voltages over the micro- to milli-seconds of time required for a complete ramp-up operation.

In addition to identifying potential design issues, RedHawk-LP with FAO (fix and optimization) allows engineers to optimize their designs to meet ramp-up timing and voltage-drop requirements. With RedHawk-LP, designers can determine the optimal size, number, and location of the MTCMOS switches to control leakage, while maintaining the integrity of the design. RedHawk-LP allows designers to determine the best strategy for turn-on timing of the switches to meet the chip’s performance and power requirements. RedHawk-LP also provides the ability to automatically remove ineffective decaps and switches, thus reducing excessive leakage caused by devices that do not contribute to the overall power integrity of the chip.


Instance-based Multi-Vdd/Vss and Multiple Voltage Domains
RedHawk-LP supports cells with multiple Vdd and Vss that are typically found in level-shifters, retention flip-flops, and memories for multi-voltage domain designs. This common low power design technique enables engineers to control and trade off power consumption and performance. RedHawk-LP enables designers to analyze the current profile and power distribution for each of the voltage domains by concurrently simulating multiple voltage islands within a full-chip context, thus delivering more accurate and realistic results.


Complete Low Power Design Integrity
“Apache is a leader in dynamic power integrity with 100s of successful power tape-outs by over 40 customers worldwide,” said Andrew Yang, CEO of Apache. “As designs move beyond 90nm, leakage management will become a key concern for designers and Apache is addressing this need by delivering a complete low power solution that enables silicon success and increased yield.”

Apache Design Solutions, NSPICE, RedHawk, PsiWinder, and Vectorless Dynamic are trademarks of Apache Design Solutions, Inc.