- RedHawkSoC Dynamic Power, Advanced Low Power, Reliability, and Chip-Package Co-design
- PowerArtistRTL Power Reduction, Analysis, Debug, and RPM Generation
- TotemAnalog/Mixed-Signal Dynamic Power, Substrate Noise, EM, and ESD
- PathFinderESD Planning, Verification and Sign-off
- Sentinel-SSOI/O DDR Power Noise and Timing Analysis
- Sentinel-TIThermal Simulation and Mechanical Stress Integrity Analysis
- Supported Platforms
- ResourcesTechnical Papers, Presentations, Contributed Articles,Conference Papers, Webinars, Videos
The proliferation of high-performance mobile devices — such as smartphones and tablet computers — along with the trend toward smaller electronic systems are driving engineers to design and deliver more power-efficient products with extended battery life, while still satisfying increasing performance requirements. Meanwhile, rise in power consumption and electricity costs from the IT infrastructure required to support growing mobile connectivity demands more energy-efficient products. In addition, the explosion in system-to-system wireless communications is amplifying the amount of noise within and between ICs, threatening the system with malfunction or failure.
The Apache suite provides innovative power analysis and optimization solutions that enable engineers to design and deliver products meeting stringent power specification limits, while still reliably and consistently delivering power to the entire system and mitigating failures or performance degradation caused by power-induced noise. Apache’s comprehensive suite of integrated software and methodologies spans a full spectrum of power, noise and reliability solutions, including power reduction, power and signal integrity, thermal management, and EM, ESD and EMI verification, from early in the design phase through final system sign-off.
Apache’s differentiated platforms address the unique challenges associated with various phases of the IC and electronic system design process, including RTL-level power budgeting; IP power delivery integrity validation; SoC integration and power noise sign-off; and IC package/board power and signal integrity, reliability verification and cost optimization. Apache’s accurate and compact models enable RTL-to-silicon, analog-to-digital, and chip–package–system power methodologies that facilitate effective coordination among multiple engineering teams and help to drive the electronic ecosystem.
The combined Apache and ANSYS suite provides even more functionality. It enables R&D teams to solve chip power delivery problems, package/board thermal/electromagnetic extraction, system enclosures and time-domain circuit analysis. Multiphysics capabilities impart the ability to simulate various physical phenomena across chips, packages and systems, including power optimization, signal integrity, electrostatic discharge (ESD), electromagnetic interference/electromagnetic compatibility (EMI/EMC), heat transfer, fluid dynamics and structural mechanics. The multi-user aspect provides the simulation platform and collaboration tools that enable electronics, electrical and mechanical engineers — along with managers and executives from different divisions within the organization — to collaborate in designing increasingly complex products.