Chip-Package-System User Group

Design enablement for low-power, high-performance, and cost-effective products requires collaboration across multiple design disciplines. As technology and complexity continue to advance, an eco-system of foundries, IP providers, ASIC designers, package vendors, and system houses is needed to help address the power, noise, and reliability challenges. The eco-system requires accurate yet efficient modeling technology to help facilitate a streamlined data exchange across multiple disciplines.

 

Eco-system data/model flow

CPS User Group aims to bring Chip, Package, and System designers together to exchange ideas, information, best practices, and feedback that will enable successful Chip-Package-System Co-design and Co-simulation needed for addressing the growing challenges of power, noise and reliability convergence. In addition, this User Group hopes to drive the standardization for creation, use and analysis of chip models that enables streamlined data exchange between chip and system groups/companies to meet multiple analysis goals.

To join CPS User Group,  please go to LinkedIn to sign-up. Your acceptance to the group will require approval by the Moderator and is pursuant to the Group Rules and Guidelines.


Chip Power Model (CPM™) Reference Flow

As a member of the CPS User Group, you will have access to the CPM Reference Flow document which provides standard procedures and recommendations on the usage of Chip Power Model to facilitate system level analysis including power delivery and EMI noise analysis.  This document was created through the collaboration of current CPS User Group members. The guidelines cover:

  • CPM model variations
  • CPM generation
  • CPM validation
  • Connection of a CPM to various system models
  • System-level analysis

The CPM Reference Guide is also available to active Apache customer through the Apache Support Center. Active Customer Support Account is required.