Totem Resources

Following is a list of whitepapers available for the Totem platform. Access to these documents requires an Apache account. If you already have an account, please login. If you wish to request a new account, click on the Whitepaper you are interested in and you will be taken to the account registration page. Please allow 24 hours for access to Apache resources.

Whitepapers

• Electronic Power and Thermal Management
  This paper presents a comprehensive set of tools and methodologies that can contribute to addressing the challenges of thermal and power management encountered in next-generation unmanned systems

• Power and Noise Integrity for Analog/Mixed-Signal Designs
  This paper describes the need for power noise integrity solution for analog / mixed-signal designs and the benefits of the Totem platform, its usage model in a design flow, and results from simulation and correlation measurements.

• PathFinder™: A Dynamic and Static Analysis Solution for IP and Full-chip IC ESD Integrity
  This paper describes how PathFinder helps designers meet ESD guidelines and identify “weak” areas of the design (layout or circuit) most vulnerable to ESD failures. It also demonstrates how PathFinder can be used for early prototyping and design exploration, especially when clamp cells are inserted inside the core region of the chip.

• Power and Signal Line Electromigration Design and Reliability Validation Challenges
  This paper describes EM integrity analysis for power and signal lines. It outlines the various process and design trends that are increasing the likelihood of EM induced failures in a design and looks at conventional verification techniques for EM integrity and contrasts those with what is required for advanced process nodes.

Webinar Presentations

• Totem™ - Analog/Mixed-Signal Power Noise and Reliability
  This webinar describes how Totem  addresses the challenges associated with global coupling of power/ground noise, substrate noise, and package/PCB capacitive and inductive noise for memory components such as Flash and DRAM, high-speed I/Os such as HDMI and DDR, and analog circuits such as power management ICs.

• PathFinder™ - Full-chip ESD Integrity and Macro-level Dynamic ESD
  This webinar describes how PathFinder provides integrated modeling, extraction, and simulation capabilities to enable automated and exhaustive analysis of the entire IC, highlighting areas of weaknesses that can be susceptible to ESD induced failure. PathFinder also delivers innovative transistor-level dynamic ESD capabilities for validation of I/Os, analog, and mixed-signal designs.

• Reliability Analysis and Modeling for SoC and Custom Designs
  This webinar describes EM analysis methodology of digital (SoC/ASIC) and custom/analog (IPs/macro) designs using Apache’s RedHawk and Totem platforms, a comprehensive analysis framework for accurate power and signal EM verification. The presentation will include discussions on advanced process and foundry EM rules, as well as self-heat analysis.

• ESD Integrity and Verification using PathFinder
  This webinar discusses ESD verification methodology at the full-chip and IP levels from early stage to sign off using PathFinder, the industry’s first ESD physical integrity solution. The presentation will include discussions on static rule based resistance checks and current density checks.