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Totem-MMX
Totem-MMX is a transistor-level power noise analysis and verification solution addressing static and dynamic power integrity needs from early design stage to sign-off validation. It addresses the verification of IPs designed using full-custom or semi-custom techniques for both analog and mixed-signal designs. Totem enables designers to verify power grid connection problems, identify high voltage drop causing mechanisms, and isolate electro-migration bottlenecks.
Key Benefits
- High design coverage and analysis accuracy for quality power, noise, and reliability signoff
- Electro-migration signoff supporting industry standard and advanced process technology EM limit
- Grid weakness check, “hot spot” root cause identification, and design fix exploration delivering significant time savings and productivity enhancements
- User friendly, layout-based unified environment for improved analysis effectiveness
Key Functionalities
- Full-chip capacity with SPICE-level accuracy for transient power/ground noise analysis
- Concurrent analysis of noise propagation through power delivery network, substrate network, and package/PCB parasitics
- Built-in extraction and simulation engine with fast incremental and “what-if”
- Layout-driven analysis integrated with existing analog design environment
- Model generation capability for hierarchical full-chip and system-level simulation
- Power and signal electro-migration validation
Power Noise Impact on Analog/Mixed-Signal Designs
With increasing frequency requirements on custom IPs, there is a need to use aggressive design styles such as placing transistors closer together, switching them faster, and eliminating margins. However, these techniques have resulted in higher switching current requirements, both temporally and spatially, and thereby injecting noise into the power and ground network, as well as the substrate.
Dynamic power and ground noise can affect reliable operation of circuits in several ways including hold-time/setup-time violations, “state-upset” in memory cells, delay push-outs in high-performance I/Os, etc. In order to address the issues associated with power noise on analog / mixed-signal designs, a new methodology and tools that delivers full-chip capacity, SPICE-level accuracy, integrated layout-driven flow, and the ability to generate accurate and high performance IP models for SoC analysis are needed.
Existing SPICE and fast-SPICE based solutions do not deliver the capacity and performance required to handle the complexities of power/ground RLC network with the transistor-level netlist. It is a single point tool that requires separate extraction engine and manual interaction to generate a netlist for simulation. In addition, it does not support incremental ‘what-if’ analysis without making layout changes, and does not support a hierarchical design methodology.
Accuracy and Capacity
Totem-MMX incorporates transistor-level modeling with voltage de-rated switching current techniques, and spice-accurate decoupling capacitance extraction for highly accurate power noise analysis. It pre-characterizes the circuit using the SPICE netlist, device models, and input vector set, and is simulated using industry standard SPICE simulators. The characterization process captures switching current waveforms for all switching transistors as a function of voltage for various operating conditions, as well as their intentional and intrinsic capacitance. It also considers the impact of package and board RLC through the support of broadband S-parameter package and PCB models.
Figure 1: Circuit modeling for PG noise simulation
Totem-MMX delivers the capacity required for standalone DRAM, Flash, and CMOS image sensors, as well as embedded memory macros. It leverages RedHawk’s MPR (Mesh Pattern Recognition) extraction technology and multi-core simulation engine to handle designs of hundreds of millions of transistors.
Layout-based Unified Analysis and Debugging Environment
Totem-MMX offers advanced viewing, debugging, and fixing capabilities to effectively analyze and optimize full-custom designs. Its layout-driven interface is integrated with existing analog design environments, supports cross-probing of power noise violations with the industry standard layout schematic tools, and interactively analyze the fixes made in the design.
Figure 2: Totem-MMX GUI shows cross probing of device to result map and GDS
The powerful ‘what-if’ capability within Totem-MMX allows designers to quickly verify a fix before committing to the layout. Fixes such as decap insertion and addition or removal of metal or via can be verified using incremental extraction and re-analysis to ensure that the proposed change does indeed fix the violation.
Figure 3: “What-if” feature for upsizing wire width to fix the IR drop
IP Creation and SoC-level Analysis
Totem-MMX provides the capability to analyze and validate power noise issues at the IP level and generate a model of that IP that can be used in SoC or top-level power noise analysis. Totem-MMX incorporates top-level connectivity and noise coupling scenario for its block/IP-level analysis. Once validated, a detailed model capturing layout and circuit behavior of the IP is generated.
Figure 4: IP creation flow
Totem-MMX generated IP model - Custom Macro Model (CMM) captures different operating states of the block such as “read” and “write” with its associated current and other parameters. It also enables designers to embed constraints such as maximum voltage drop allowance on transistors or a metal layer in the model for top-level verification.
Figure 5: Current waveforms in different operating states captured in IP model
To support multi-company IP integration, Totem-MMX provides various levels of IP encryption to protect the intellectual property of the circuitry. It delivers an optimized model for quick top-level analysis, while preserving the overall integrity without compromising its accuracy.
Power and Signal Reliability Analysis
Totem-MMX provides a single platform for power rail and signal interconnect electro-migration (EM) analyses. Power EM is performed as part of static or dynamic analysis.
It supports industry standard and technology EM limit for 65/45/28nm processes and provides checks for average, RMS and peak current densities. The EM results are easily checked and analyzed in the layout-based environment.
Figure 6: Integrated views of EM result table and violation
Signal EM analysis is performed for average, RMS, and peak current densities in all signal wires and vias. It supports unified run with separate uni-directional and bi-directional current analysis. Totem-MMX either estimates the current based on design parameter and user input or imports the current based on actual SPICE simulation. It uses simulation-based current modeling for accurate dynamic analysis.
Totem-MMX analyzes Signal EM checks on flattened transistor-level designs as well as on block-level inter-cells for embedded digital blocks. It can support separate limits for average, RMS, and peak currents. Its layout-based GUI with cross probing capabilities provides easy to use and robust debugging including detailed violation reports with current values and their direction.
Figure 7: Signal EM debugging – searches shortest path of resistance (SEM violation location to all pads)
Connectivity Weakness Exploration
Totem-MMX provides the capability to verify grid connectivity issues, such as missing vias and weakly connected devices. These connectivity issues can be debugged using the GUI and textual reports. Totem-MMX’s network topology analysis provides insights into routing issues that can cause voltage drop hot-spots or current congestions in the design. The shortest electrical path from the voltage supply pads to every transistor is provided as an overlay on the design layout allowing one to identify the bottleneck segments.
Figure 8: Integrated views of transistor pin resistance and its minimum resistance path
Integrated Power Noise Integrity Solution for Analog/Mixed-Signal Designs
Totem-MMX is a comprehensive solution that incorporates transistor-level noise injection, parasitic extraction, package modeling, dynamic analysis, and design debug in a single-flow environment to enable analog/mixed-signal designers to mitigate design failure risks and reduce the product cost.
