- Products
- PowerArtistRTL Power Reduction, Analysis, Debug, and RPM Generation
- RedHawkSoC Dynamic Power, Advanced Low Power, Reliability, and Chip-Package Co-design
- TotemAnalog/Mixed-Signal Dynamic Power, Substrate Noise, EM, and ESD
- SentinelChip-Package-System Power/Signal Integrity, IO-SSO, Thermal, and EMI
- ResourcesTechnical Papers and Presentations, Contributed Articles and Conference Papers, Webinars and Videos
- Flows
- Ultra Low PowerPower methodology for ultra-low-power designs
- IP IntegrationPower methodology for IP Integration initiative
- Chip-Package-SystemPower methodology for giga-hertz performance
- Support
- Community
- CustomersServing the industry’s leading electronics companies
- PartnersFoundry, IP, EDA, Industry Alliances
- Blog
- Chip-Package-System User GroupConvergence for Power, Noise, and Reliability
- Company
- About ApacheOverview, Milestones, Achievements
- News
- Events
- Employment
- Global Offices
Totem-EX
Totem-EX provides proven device-level, RLC parasitic extraction for custom designs. It accepts LVS geometry and netlists from Calibre, Assura, and Diva, extracts parasitics, and produces reduced, simulation-ready netlists.
Designers of VCOs, SERDES, radios, and other high-frequency analog and quasi-digital circuits use Totem-EX inductance extraction to predict the impact of parasitic loop and mutual inductance on circuit performance. Designers can limit inductance extraction to RF paths, to avoid needlessly complex parasitics that slow simulation to a crawl.
Designers of high-performance digital circuits use Totem-EX to accurately extract parasitics around transistors and other devices. Totem-EX allows precise control over which parasitics to model around each device type, to match the parasitics already included in device’s SPICE model. It resolves capacitance around contacted MOS transistor with best-in-class, sub-fF accuracy.
Key Benefits
- Predict how parasitic inductance affects high-frequency designs using proven, efficient loop- and mutual-inductance modeling
- Reduce simulation time while maintaining accuracy with selected-net extraction, mixed-mode parasitic models, and user controlled parasitic reduction
- Avoid double-counting or omitting parasitics around devices, by precisely controlling which parasitics to include during extraction, even around 40nm MOS transistors
- Model differential and iterated circuits with parasitics that don’t change when reflecting or rotating identical layouts
- Maximize productivity and minimize learning time with a complete Virtuoso integration, including cross-probing and interactive RLC parasitic probing
- Leverage existing investments in Calibre, Diva, and Assura through integration with multiple LVS tools
- Accurate, compact, and high-fidelity parasitic extraction
- Electromigration (EM) analysis
- Virtuoso integration and LVS support
Key Functionalities
- Accurate, compact, and high-fidelity parasitic extraction
- Electromigration (EM) analysis
- Virtuoso integration and LVS support
Accurate, Compact, High-fidelity Parasitics
Custom designers face a dual challenge with post-layout parasitics: getting sufficient accuracy for analyzing their designs without exceeding the runtime or capacity limitations of downstream tools. Totem-EX addresses both constraints, with the features needed for accuracy for both analog and digital design, and with controls that allow the designer to reduce the complexity of parasitics in ways that match his design goals.
Analog designs pose many extraction challenges. High-frequency designs such as SERDES blocks include differential RF paths whose stability and performance are affected by on-chip inductance. Differential circuits require symmetrical parasitics to avoid unrealistic DC offsets and AC imbalances. RF FETs and resistors already include some parasitics that must not appear again in interconnect parasitics. They also include interconnect idioms, such as via-filled low-resistance nets, that can explode the size of parasitics.
Figure 1: Emitter follower oscillates due to parasitic L
Figure 2: Layout of via-filled low-R line
In addition to providing accurate analog parasitics, Totem-EX provides direct control over how it models parasitics. From the GUI, the user can extract selected groups of nets within different modes with varying reduction levels. For example, in a single extraction run, a designer can extract RF paths as detailed RLCK, bias and other lower-frequency nets as RC with R < a given threshold reduced, and power rails as coupled-C only, and create a complete, coupled parasitic netlist across the groups.
Figure 3: Mixed-mode model
Digital designs pose particular challenges for modeling contacted MOS transistors, especially for 40nm or 45nm processes. Miller capacitance can significantly affect the speed of circuits, from ring oscillators to embedded memories. Totem-EX can extract interconnect parasitics, including contact capacitance for logic and DRAM processes, that match the design’s MOS SPICE model, giving superior correlation to hardware measurements.
Figure 4: Contact capacitance for a MOS transistor
Analyzing Electromigration
Nets in custom layouts include a much wider variety of shapes than those created by routing algorithms. Narrow points in wires occur accidentally, when hand-drawn or –placed shapes overlap or align imperfectly, and these inadvertent “fuses” can cause EM failures.
Totem-EX creates accurate EM parasitics that allow the user to find all potential EM problems in custom layouts. Besides annotating the resistors that represent the usual rectangular wires and via/contact arrays, it adds “fuse” resistors of appropriate width for narrow points. It handles many cases that other extractors may miss, including offset wires and malformed L and T junctions. EM checkers using these parasitics can then test current-density violations at the fuses.
Figure 5: “Fuse” resistors (n) for electromigration analysis
Virtuoso and LVS Support
Virtuoso users can control Totem-EX completely from within the Virtuoso GUI. The Totem-EX ’ Virtuoso GUI creates complete Virtuoso extracted views, sufficient for all usual uses, including netlisting, simulation, probing parasitic RLC, and EM analysis. It also supports schematic cross-probing and RLC parasitic probing.