- PowerArtistRTL Power Reduction, Analysis, Debug, and RPM Generation
- RedHawkSoC Dynamic Power, Advanced Low Power, Reliability, and Chip-Package Co-design
- TotemAnalog/Mixed-Signal Dynamic Power, Substrate Noise, EM, and ESD
- SentinelChip-Package-System Power/Signal Integrity, IO-SSO, Thermal, and EMI
- ResourcesTechnical Papers and Presentations, Contributed Articles and Conference Papers, Webinars and Videos
CSE adds substrate extension to the Totem product. It is the only commercially available solution for modeling and simulating substrate-based noise coupling at the full-chip level. It includes extraction of the substrate network for advanced process technologies and provides an integrated and concurrent time-domain simulation of the substrate network along with power/ground mesh and package parasitics. CSE accounts for the full-chip SoC substrate noise effects by directly interfacing with RedHawk to obtain accurate substrate injection signature of all digital components.
CSE enables analog and RF designers to accurately determine the magnitude of substrate coupling effects and evaluate the effectiveness of their substrate isolation mechanisms.
Substrate Noise Impact on Analog/Mixed-Signal Designs
Even though analog and digital circuits are isolated through different power and ground supplies on the die, they are etched on the same silicon substrate. This results in high switching digital core impacting the performance of the noise sensitive analog circuits. Designers employ different isolation techniques to separate the digital and analog circuitries with varying effectiveness, and with no formal analysis and verification solutions available to model and predict the substrate coupled noise; the designers are forced to use rule-of-thumb based techniques. The ability to accurately analyze substrate noise coupling is critical for high-performance mixed-signal and radio frequency (RF) designs.
Figure 1: Cross sectional view of IC including substrate
Full-chip Substrate Noise Coupling
CSE enables designers to model and simulate the substrate-based noise coupling at the full-chip level by considering the substrate RC network as a propagation medium of noise between a high performance digital logic and noise sensitive analog circuit residing on the same die. The analysis is performed in conjunction with on-die power/ground RLC network and package/board parasitics to help designers evaluate different substrate isolation mechanisms.
Leveraging the full-chip substrate noise coupling analysis provided by CSE, designers can optimize for better performance, lower product cost, prevent design failures, or meet functional or timing specifications.
Noise Coupling Prediction
To predict the possible coupling of sensitive RF circuit operating at a particular frequency and the noise spectrum of high energy around the same frequency, the designers can observe the current waveform generated by simultaneous simulation of digital and analog blocks and probe the layout to obtain the frequency content of the noise in any portion of the design.
Figure 2: Noise coupling scenario
The accuracy of this analysis is dependent on the ability to simultaneously consider the entire design with all noise sources and propagation medium. It also requires time-domain simulation at pico-second resolution for a long duration of time at the full-chip level. CSE is the only tool available with the capacity to meet these requirements and can provide the information necessary to understand the power/ground network-driven noise coupling.
Isolation Technique Selection
CSE considers all substrate layers and the necessary technology parameters in constructing the substrate RC network, as well as models all the pertinent noise injection mechanisms such as standard cells, memories, I/Os, analog and custom circuits. This enables designers to use CSE analysis for judging the efficacy of the various substrate noise isolation structures.
Figure 3: Various isolation techniques
Back-annotation to IP Simulation
CSE SoC analysis with noise injection from various circuits including digital and analog components and propagating through on-die, package, and substrate parasitic networks produces accurate supply voltage noise signature for IP-level simulation. Traditionally, these simulations are performed using constant supply voltage for various power/ground pins. By using CSE generated voltage waveform, the designers can explore the impact of coupled noise on their IP and determine if additional changes to the layout or protection schemes are needed.
Figure 4: Back-annotated IP simulation flow
Frequency Domain Noise Injection and Propagation
CSE provides user with the ability to inject noise waveform and simulate to see how that noise propagates through the substrate and appears at the isolation structures of the sensitive analog circuits.
Figure 5: Frequency domain analysis
A frequency domain based response to the injected noise is provided to the user following the SoC simulation. The injected noise pattern can be defined by the user or CSE's default step input noise waveform can be used. Reports and graphical displays are provided showing the amplitude of the propagated noise at various frequency points.