- PowerArtistRTL Power Reduction, Analysis, Debug, and RPM Generation
- RedHawkSoC Dynamic Power, Advanced Low Power, Reliability, and Chip-Package Co-design
- TotemAnalog/Mixed-Signal Dynamic Power, Substrate Noise, EM, and ESD
- SentinelChip-Package-System Power/Signal Integrity, IO-SSO, Thermal, and EMI
- ResourcesTechnical Papers and Presentations, Contributed Articles and Conference Papers, Webinars and Videos
The trend toward multi-die integration has increased IC functionality and speed. For advanced package designs such as PoP, Stacked-die SiP, 3DIC/TSV, etc., heat dissipation and the thermal characteristics play a significant role in chip reliability. Critical factors impacting IC reliability is determined by both IC and packages. At the system level, reliability on thermal stress depends on matching the thermal expansion properties of the die, interconnects, package and PCB to avoid thermal differential expansion due to internal or external temperature changes.
Figure 1: Typical configuration of chip/package on board with external heat sink
Sentinel-TI (Thermal and mechanical Integrity) is an integrated die/package/board thermal and thermal/mechanical stress analysis solution. It provides unparalleled accuracy and ease-of-use on a variety of both custom and industry-standard package styles. Its unique capability of taking Chip Thermal Model (CTM) from RedHawk/Totem enables users to get accurate on-die temperature variation in very fine resolution, as well as layer-by-layer temperature profile. Apache’s RedHawk/Totem solutions can read the output from Sentinel-TI to perform temperature dependant electromigration (EM) analysis, as well as accurate leakage power calculation.
Figure 2; CTM-based thermal analysis generates accurate on-die power and temperature variation in very fine resolution including layer-by-layer temperature profile.
- Chip power and temperature convergence with consideration for chip-package-PCB environment
- CTM-based thermal analysis provides converged temperature map for accurate RedHawk on-chip power and EM analysis
- Efficient model generation including trace/via details for best modeling accuracy
- Highly efficient solver for large matrix capacity
- Fully automated CAD Link modeling for ease of use and SiP support
- Single platform for thermally induced stress and other reliability analyses
- IC-aware chip-package thermal co-analysis using Chip Thermal Model (CTM)
- Export converged on-chip temperature profile for RedHawk/Totem analysis
- Package and PCB mesh generation including trace/via distribution details
- JEDEC thermal resistance model extraction (Theta-JA, JB, and JC, and DELPHI)
- Thermal influence coefficient matrix extraction for SiP
- Early-design analysis for BGA, leadframe, and SiP
- Fully automated CAD Link modeling for SiP
- Thermal analysis of PCB with multiple components
- Thermal stress analysis
- Package reliability analyses, including warpage, solder joint fatigue, drop, die-cracking, popcorning, and delamination
Simulating the effects of thermal and thermal/mechanical stresses on a particular IC package requires a detailed finite element model of the package with all package parameters. The models used in Sentinel-TI are configured according to the design information and specifies the corresponding loading conditions, including power, ambient temperatures, etc. The models are solved using an accurate and efficient numerical solver and the analysis results (including temperature distribution) are graphically highlighted to demonstrate the package behavior under the specified analysis conditions. The simulation results are also available in the form of a detailed text file report.
Figure 3: Simulation flow of CTM-based thermal analysis and thermal stress analysis
Chip Thermal Model (CTM)
For designs at 65nm technology node and below, analyzing and managing leakage current has become one of the key design challenges for a successful high performance design. Leakage current is known to be strongly (exponentially) dependent on temperature. Hence to accurately analyze individual instance leakage currents, designers need to consider temperature variation across the chip produced by uneven power consumption. Local chip temperature also affects the metal resistivity, interconnect self-heating, and EM/voltage drop in the design. After thermal-power iterations, the total power and maximum temperature variations could be more than 20% in some devices.
Figure 4: Leakage power and its dependency on temperature; Power-Thermal iterations for PT convergence
Sentinel-TI is a Chip-Thermal-Model (CTM) based thermal analysis solution offering the industry's first fully integrated power-thermal iterative solution for analyzing the thermal impact on leakage. Sentinel-TI makes use of accurate temperature-dependent chip-power database in CTM, along with the detailed package-on-board thermal model, to predict the on-chip power and temperature convergence map. The tightly integrated CTM-based thermal analyses deliver accuracy, capacity, performance, and ease-of-use for fast convergence of power and thermal distribution.
After thermal-power convergence, the temperature gradient on a chip can be 2 to 5 times greater than the results obtained by using a simplified assumption of uniform power on a chip. The picture below shows an example of converged power and temperature maps on a chip.
Figure 5: Converged power and temperature maps on a chip
Sentinel-TI allows design engineers to quickly and easily construct complex, finite element simulation models for various types of electronic package designs. It offers convenient built-in parametric modeling for standard JEDEC packages. The user-friendly GUI enables the designers to define a physical package by providing only the package dimensions and preferred material properties. The material properties can be obtained from the extensive library embedded within Sentinel-TI. To ensure correct data entry, an illustration of all the parameters that are required for each data entry screen is provided such that the meaning of the parameter is never in question.
Sentinel-TI’s extensive internal database of semiconductor packages covers both leadframe and BGA types of package designs. In addition, the Direct Cad Interface (DCI) to Cadence MCM/SIP files and Gerber files can be used to construct non-standard package models and create detailed metal traces in the substrate/PCB. Supported package types include: Ball Grid Array (BGA), Quad Flat Package (QFP), Dual Inline Package (DIP), Small (or Short) Outline (SO), Plastic Leaded Chip Carrier (PLCC), Chip Scale Package (CSP), Flip Chip Package, and Quad Flat No Leaded Package (QFN).
For accuracy, detailed traces and vias are included in the analysis model. Thermal results from a simplified or smeared metal layer model could vary up to 30% from that with detailed traces and vias. This feature is equally important in thermal stress analysis for package reliability.
Figure 6: Modeling details of substrate metal traces and vias
The temperature at which a package operates determines the service life of a device since excessively high temperatures degrades the chemical and structural integrity of various materials used in the packaging. Sentinel-TI can be easily set up to run various temperature related analysis for both single chip and multi-chip modules including θja, θjb and θjc analysis at different air speeds and power dissipation calculations for the package top, sides and PCB. Heat transfer coefficients assigned to external surfaces are based on experimental results. This produces more practical boundary conditions in the analysis than simulated ones. Detailed package modeling, including metal trace and via considerations, results in a more accurate prediction of thermal responses.
Influence coefficient matrix in SiP, which is equivalent to θja for single chip package, could also be automatically extracted in Sentinel-TI. Similar to ‘Power x θja = ΔT’ for a single chip package, the formula for SiP with n chips is shown below where elements in the A matrix are the influence coefficients. Different power allocations (P) on the chips provide different temperature rise (ΔT), respectively.
Sentinel-TI extracts DELPHI compact thermal model which provides the thermal resistance network used in system-level simulation.
Figure 7: DELPHI compact thermal model extraction in Sentinel-TI
Sentinel-TI can also extend the thermal analysis from package to multiple packages on PCB by including the details of metal traces on PCB in the analysis.
Figure 8: Thermal analysis of PCB with multiple packages
Thermally Induced Stress
Sentinel-TI is a valuable tool for evaluating the thermally induced deformation and stress in the IC package due to die heating. Sentinel-TI uses the temperature distribution in the package calculated by thermal analysis as the loading for deformation and stress analysis. It automatically performs a coupled-field analysis (i.e. a thermal analysis followed by a structural analysis). The results include θja;Ψjt; and heat dissipation through the package top, side and PCB and demonstrate the warpage of a package and component stresses caused by thermally induced stress condition.
Figure 9: Package deformation and component stress information provided by thermal stress analysis
Trends in IC packaging are towards mounting larger dies on to smaller and thinner substrates. Since the package thickness is very small, internal stresses can cause external deformation, the so-called warpage phenomenon. Warpage changes the lead co-planarity that significantly influences the assembly process. Sentinel-TI provides a powerful set of tools that allows designers to accurately estimate the warpage deformation in different parts of a package, enabling them to choose suitable materials and assembly processes to minimize warpage and the internal residual stresses.
Figure 10: Displacement vectors showing warpage of package; Stress on metal traces identifying critical locations for reliability check
As small handheld devices are popular, effects of drop of package/board becomes a common reliability issue. Sentinel-TI automates the boundary condition setup to simulate JESD22-B111 drop test conditions. Evaluation of stresses on package components can be performed easily through the response contours.
Figure 11: Deformation and stresses information provided by drop analysis
Solder Joint Reliability
Differential thermal expansion of components in a package and the PCB can result in 2nd level interconnection reliability issues. Accelerated Thermal Cycling (ATC) and Power Cycling are common tests used to evaluate the package reliability based on solder joint fatigue Sentinel-TI’s easy setup and automated analysis process enables designers to calculate life cycles of a package.
Figure 12: Automated setup and evaluation of solder joint reliability
Sentinel-TI performs post-processing analysis to estimate the effects of residue stresses due to warpage, moisture influence, component interface delamination, popcorning, and die cracking.
Sentinel-TI provides the following outputs from package / PCB thermal integrity analysis.
- θja, θjb, θjc, Ψjt DELPHI model
- Thermal stresses
- Die cracking prediction
- Delamination prediction
- Popcorning level prediction
- Solder joint fatigue life prediction
Sentinel-TI supports Gerber, Cadence (.mcm, .sip, and .brd), UPD, Mentor Graphics MCM Station and Zuken CR-5000 package designs.