- PowerArtistRTL Power Reduction, Analysis, Debug, and RPM Generation
- RedHawkSoC Dynamic Power, Advanced Low Power, Reliability, and Chip-Package Co-design
- TotemAnalog/Mixed-Signal Dynamic Power, Substrate Noise, EM, and ESD
- SentinelChip-Package-System Power/Signal Integrity, IO-SSO, Thermal, and EMI
- ResourcesTechnical Papers and Presentations, Contributed Articles and Conference Papers, Webinars and Videos
Sentinel-SSO is a high-capacity I/O sub-system timing and noise analysis solution targeted for IC and package SI designers. It imports the physical design data (LEF/DEF/GDS) of the chip I/O ring, performs parasitic extraction and macro-modeling and runs transient simulation of selected banks of I/O interface, particularly under the simultaneous switching condition. To ensure measurement quality and sign-off accuracy, Sentinel-SSO supports RLCK, transmission line models and S-parameter based package and PCB models. With a graphical user interface and TCL based command line interface, the designer can efficiently build an I/O subsystem including on-die physical design and its system level connections to package and PCB models for I/O timing and jitter simulation at both early design and sign-off stages. System level connectivity also includes power supplies, terminations and receiver models, in addition to the complete package and PCB channel. Sentinel-SSO’s macro-modeling technologies enable designers to achieve fast turn-around time during design iterations and perform what-if analysis and assess the effectiveness of on-die power grid routing, on-die decoupling capacitors placements, package/PCB channel quality and Power Delivery Network (PDN), as well as the signal to power and ground ratios.
Figure 1: I/O Subsystem Noise and Timing Analysis Scheme
- Peform I/O noise and timing sign-off
- “What-if” analysis for on-die decap optimization
- Determine the effectiveness of global PDN and decoupling
- I/O physical layout based automated simulation flow
- Advanced macro modeling technology for capacity and speed
- Integration of channel model from Sentinel-PSI
- Comprehensive JEDEC compatible results reporting
I/O Physical Layout-based Automated Simulation Flow
Sentinel-SSO provides an I/O physical layout-based automated flow for I/O subsystem signal and power integrity with built-in on-die power grid RLC extraction and on-die decap characterization. The on-die power grid (including Redistribution Layer) extraction engine is proven to be accurate and robust and has been used in RedHawk’s power integrity sign-off for the hundreds of tapeouts. Through a configuration file and TCL command interface, the users can
- Import a selected region of I/O bank for extraction and simulation
- Connect a package/PCB channel model to the I/O bank
- Assign stimulus and specify observation, termination and receiver models
- Display waveform, generate eye-diagram and make jitter measurements
Figure 2: Full-chip view (left) and zoomed-in view of one of I/O region with on-die power grid (right)
Figure 3: Eye-diagram output
Advanced Macro-modeling Technology for Capacity and Speed
One critical challenge in global I/O-SSO simulation is transistor level timing accuracy and the complexity of the global PDN and signal channel models. For a bank of the I/O, the on-die power grid extraction may yield ten million plus electrical nodes, but Sentinel-SSO reduces the complexity of the circuit simulations through the following built-in advanced macro-modeling algorithm:
- Broadband model reduction of on-die PDN
The extracted on-die RLC network is reduced to a behavior model preserving the terminal behavior of the on-die and package PDN connectivity, as well as the I/O cell power/ground pins. Unlike the traditional on-die RC screening method based reduction, Sentinel-SSO employs an AC frequency analysis based model order reduction that can maintain the accuracy up to the specified maximum frequency (default 5GHz). With the reduced-order modeling, Sentinel-SSO delivers the industry’s first I/O timing and noise analysis that can accurately account for the on-die parasitics.
- Macro-modeling of power noise aggressor I/O cells
Complex I/O transistor models are another bottleneck for the global SSO simulation. In Sentinel-SSO, “victim”, “cross-talk aggressors”, and “power noise aggressors” concept is introduced to establish a “victim” centric, parallel simulation scheme. The power noise aggressors are identified for a specific victim and macro-modeled with non-linear behavioral equivalent circuits. Typically, a speed-up of 2X to 5X can be achieved through power noise macro-modeling, while preserving the jitter simulation accuracy within 10%. This enables a much faster turn-around time for SSO simulation used in design iterations.
Integration of Channel Model from Sentinel-PSI
An accurate channel model encapsulating both signal integrity and power integrity is crucial for the accuracy of I/O noise and timing simulation. Sentinel-SSO supports lumped and distributed models (RLCK and T, W) as well as the S-parameters. Sentinel-PSI, the high capacity next generation 3D fullwave solution, has a built-in “SSO Channel Builder” to allow one-button channel model library generation that is customized for Sentinel-SSO simulation. For a particular victim net and crosstalk aggressor nets identified by Sentinel-SSO, the SSO Channel Builder extracts a reduced-order and optimized time-domain macro-model from the channel model library.
Figure 4: Integration of Sentinel-PSI Channel Model Library
Comprehensive JEDEC Compatible Results Reporting
Sentinel-SSO has an integrated results viewer to display various types of waveforms, as well as the eye-diagram of any particular signal. In addition, Sentinel-SSO results include a series of JEDEC compatible timing and noise measurements such as delay (self delay, setup/hold time), slew (rising edge and falling edge), noise (peak over shoot and peak under shoot), and jitter.
Figure 5: Jitter results reporting
Figure 6: Noise (Peak Overshoot and Undershoot) results reporting