- Products
- PowerArtistRTL Power Reduction, Analysis, Debug, and RPM Generation
- RedHawkSoC Dynamic Power, Advanced Low Power, Reliability, and Chip-Package Co-design
- TotemAnalog/Mixed-Signal Dynamic Power, Substrate Noise, EM, and ESD
- SentinelChip-Package-System Power/Signal Integrity, IO-SSO, Thermal, and EMI
- ResourcesTechnical Papers and Presentations, Contributed Articles and Conference Papers, Webinars and Videos
- Flows
- Ultra Low PowerPower methodology for ultra-low-power designs
- IP IntegrationPower methodology for IP Integration initiative
- Chip-Package-SystemPower methodology for giga-hertz performance
- Support
- Community
- CustomersServing the industry’s leading electronics companies
- PartnersFoundry, IP, EDA, Industry Alliances
- Blog
- Chip-Package-System User GroupConvergence for Power, Noise, and Reliability
- Company
- About ApacheOverview, Milestones, Achievements
- News
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- Global Offices
Sentinel Resources
Following is a list of documents available for the Sentinel platform. Access to these documents requires an Apache account. If you already have an account, please login. If you wish to request a new account, click on the document you are interested in and you will be taken to the account registration page. Please allow 24 hours for access to Apache resources.
Whitepapers
- Electronic Power and Thermal Management
This paper presents a comprehensive set of tools and methodologies that can contribute to addressing the challenges of thermal and power management encountered in next-generation unmanned systems
- Advanced Modeling Technologies for Chip, Package, System Co-analysis and Co-optimization
The traditional approach to chip-package-system (CPS) co-analysis and co-optimization lacks required accuracy and limits productivity. To meet the increasing demands for system cost down calls for a new methodology that is more comprehensive. This white paper outlines the Chip Power Model (CPM™) technologies and solutions available from Apache Design Solutions to help address the CPS convergence challenge.
- Technologies for Power, Signal, Thermal, and EMI Sign-off
This whitepaper discusses the challenges associated with designing smaller, faster, and lower cost products and the necessity for an analysis methodology that addresses the cross domain effect in today's advanced process designs. The paper also provides an overview of Apache's power and noise solutions and how these products enable comprehensive chip-package-system convergence flow across multiple design disciplines.
Webinar Presentations
- Sentinel™-PSI - IC-Package Power and Signal Integrity Solution
This webinar describes how Sentinel-PSI provides the accuracy of a conventional 3D full-wave tool, with the unparalleled capacity to handle an entire package or board design. Sentinel-PSI is seamlessly connected to other Apache products in system-level analysis, and is linked with Sentinel-SSO to perform system-level I/O-SSO simulations..
- IO Sub-system Timing and Jitter Analysis Considering Power and Signal Noise Impact
This webinar describes SSO analysis methodology for generating accurate timing and jitter numbers using Sentinel-SSO, a comprehensive framework that provides efficient simulation of an entire IO bank along with the package and PCB. The presentation will discuss IO-SSO simulation that includes IO, package, and board elements, as well as the consideration of both power/ground and signal networks.
- Chip Power Model: Next Generation Power Modeling Capabilities
This webinar describes Chip Power Model (CPM), an accurate and compact die model of the IC’s power deliver network, along with examples of how it is used for chip-package-system convergence. The newest functionality of CPM is presented with details on how it can provide greater verification and sign-off coverage, as well as the results of the latest options such as resonance frequency aware CPM and chip-level probing in a chip-package-system simulation.