- PowerArtistRTL Power Reduction, Analysis, Debug, and RPM Generation
- RedHawkSoC Dynamic Power, Advanced Low Power, Reliability, and Chip-Package Co-design
- TotemAnalog/Mixed-Signal Dynamic Power, Substrate Noise, EM, and ESD
- SentinelChip-Package-System Power/Signal Integrity, IO-SSO, Thermal, and EMI
- ResourcesTechnical Papers and Presentations, Contributed Articles and Conference Papers, Webinars and Videos
Following is a list of whitepapers available for the RedHawk platform. Access to these documents requires an Apache account. If you already have an account, please login. If you wish to request a new account, click on the Whitepaper you are interested in and you will be taken to the account registration page. Please allow 24 hours for access to Apache resources.
- Electronic Power and Thermal Management
This paper presents a comprehensive set of tools and methodologies that can contribute to addressing the challenges of thermal and power management encountered in next-generation unmanned systems
- Advanced Modeling Technologies for Chip, Package, System Co-analysis and Co-optimization
The traditional approach to chip-package-system (CPS) co-analysis and co-optimization lacks required accuracy and limits productivity. To meet the increasing demands for system cost down calls for a new methodology that is more comprehensive. This white paper outlines the Chip Power Model (CPM™) technologies and solutions available from Apache Design Solutions to help address the CPS convergence challenge.
- Power Noise Analysis for Next Generation ICs
This paper describes the challenges associated with power delivery network designs and how RedHawk, a full-chip dynamic power analysis tool helps designers address the design failures caused by dynamic power noise.
- Low Power Design Analysis
This paper describes the technology and methodology for analysis of designs utilizing power-gating switches for leakage control. It describes the requirements of verifying low power designs in different modes of operation, as well as in mixture of various states.
- Power Closure Flow
This paper describes a power aware physical design methodology that includes power supply planning, resource allocation, and design (package, decap, and power grid network) in conjunction with sign-off quality verification to achieve faster design closures.
- Jitter & Critical Path Timing
This paper describes the technology behind Apache's PsiWinder, which delivers standard-cell capacity and ease-of-use with Spice-accurate simulation of critical timing paths and clock tree network, including effects such as crosstalk and dynamic voltage drop.
- PathFinder™: Solution for Full-chip IC ESD Integrity
This paper describes how PathFinder helps designers meet ESD guidelines and identify “weak” areas of the design (layout or circuit) most vulnerable to ESD failures. It also demonstrates how PathFinder can be used for early prototyping and design exploration, especially when clamp cells are inserted inside the core region of the chip.
- Power and Signal Line Electromigration Design and Reliability Validation Challenges
This paper describes EM integrity analysis for power and signal lines. It outlines the various process and design trends that are increasing the likelihood of EM induced failures in a design and looks at conventional verification techniques for EM integrity and contrasts those with what is required for advanced process nodes.
- Technologies for Power, Signal, Thermal, and EMI Sign-off
This whitepaper discusses the challenges associated with designing smaller, faster, and lower cost products and the necessity for an analysis methodology that addresses the cross domain effect in today's advanced process designs. The paper also provides an overview of Apache's power and noise solutions and how these products enable comprehensive chip-package-system convergence flow across multiple design discipline
- RedHawk™ - SoC Power Integrity and Sign-off for 28-nm Designs
This webinar describes how RedHawk enables IC designers to explore and identify physical design weaknesses, automatically repair the source of supply noise, analyze the impact of dynamic voltage drop on timing, verify power and signal EM, and provide a model of the chip's power delivery network for system-level analysis.
- PathFinder™ - Full-chip ESD Integrity and Macro-level Dynamic ESD
This webinar describes how PathFinder provides integrated modeling, extraction, and simulation capabilities to enable automated and exhaustive analysis of the entire IC, highlighting areas of weaknesses that can be susceptible to ESD induced failure. PathFinder also delivers innovative transistor-level dynamic ESD capabilities for validation of I/Os, analog, and mixed-signal designs.
- Reliability Analysis and Modeling for SoC and Custom Designs
This webinar describes EM analysis methodology of digital (SoC/ASIC) and custom/analog (IPs/macro) designs using Apache’s RedHawk and Totem platforms, a comprehensive analysis framework for accurate power and signal EM verification. The presentation will include discussions on advanced process and foundry EM rules, as well as self-heat analysis.
- ESD Integrity and Verification using PathFinder
This webinar describes ESD verification methodology at the full-chip and IP levels from early stage to sign off using PathFinder, the industry’s first ESD physical integrity solution. The presentation will include discussions on static rule based resistance checks and current density checks.
- Chip Power Model: Next Generation Power Modeling Capabilities
This webinar describes Chip Power Model (CPM), an accurate and compact die model of the IC’s power deliver network, along with examples of how it is used for chip-package-system convergence. The newest functionality of CPM is presented with details on how it can provide greater verification and sign-off coverage, as well as the results of the latest options such as resonance frequency aware CPM and chip-level probing in a chip-package-system simulation.
- A Design for Power (DFP™) Methodology: Power Integrity Verification and Signoff for Low Power Designs
This webinar describes RedHawk’s extensive capabilities for analyzing low power designs, while considering the complexities associated with all these power saving features. It describes RedHawk’s capabilities for simulating static and dynamic analysis of designs with multiple voltage islands, VTH circuit styles, clock gating, and power gating. It also highlighs the low power debug capabilities of RedHawk Explorer, which can automatically identify design problems in power-gated designs.