- PowerArtistRTL Power Reduction, Analysis, Debug, and RPM Generation
- RedHawkSoC Dynamic Power, Advanced Low Power, Reliability, and Chip-Package Co-design
- TotemAnalog/Mixed-Signal Dynamic Power, Substrate Noise, EM, and ESD
- SentinelChip-Package-System Power/Signal Integrity, IO-SSO, Thermal, and EMI
- ResourcesTechnical Papers and Presentations, Contributed Articles and Conference Papers, Webinars and Videos
RedHawk-PSI is a full-chip clock network integrity (jitter) and critical path timing signoff solution for high-performance nanometer designs. It considers the concurrent and interdependent effects of power and signal integrity on clock jitter and critical path timing. Certified by TSMC's Reference Flow, RedHawk-PSI delivers cell-based ease-of-use and performance with true SPICE accuracy. With RedHawk-PSI, designers gain visibility to true silicon behavior, allowing them to focus on the real timing issues.
- Catch and fix clock tree design issues to avoid silicon failures
- Quantitatively measure clock jitter noise with silicon correlated accuracy for timing margin validation
- True SPICE accurate timing analysis on critical paths accounting for concurrent PI and SI noise impact:
- Filter false STA violations
- Increase confidence in timing sign-off
- Completely integrated inside RedHawk environment with minimal additional data preparation, allowing ease of use
- True Dynamic solution for clock jitter and critical path timing analysis
- Considers concurrent effects of power integrity and signal integrity
- Delivers SPICE-level accuracy within a cell based flow
Dynamic vs. Static
Existing timing solutions are based on static methods. However, with increasing switching frequencies and lower operating voltages as designs have moved to 65/42/32nm and below, it is no longer acceptable to ignore or approximate the “true” dynamic effects of the circuit with a static-based solution.
RedHawk-PSI is a dynamic solution with critical path analysis that is based on real signal waveform simulation versus a linear approximation (STA approach). It also uses real Vdd/Vss instance waveforms rather than effective Vdd/Vss approximation of instance supply voltages.
Figure 1: Real signal waveform simulation vs. linear approximation
Figure 2: Real Vdd/Vss instance waveform vs. effective Vdd/Vss approximation
Concurrent PI and SI
At 65nm and lower nodes, both crosstalk and dynamic voltage drop significantly impact the chip’s performance. The concurrent impact of SI and PI can be greater than the sum of individual effects.
Figure 3: Concurrent impact of SI and PI is greater than the sum of individual effects
Hence it is imperative that the timing solution accounts for both signal and power supply noise concurrently.
Figure 4: SoC noise can cause real timing failures
RedHawk-PSI reads in the design database, parasitic information, static timing report, and builds a SPICE netlist of the clock tree network and critical path. The network also includes all the coupling capacitors and the coupled aggressor gates. To determine the real fan-out load of the aggressor drivers, RedHawk-PSI uses a non-linear MOS transistor model instead of a simplified equivalent capacitance load model. This provides much higher accuracy for crosstalk noise analysis compared to other methods.
Figure 5: Real fanout transistor load vs. equivalent capacitance load approximation
RedHawk-PSI accurately represent the effects of dynamic voltage drop and ground bounce on timing by performing true dynamic transient analysis of the full-chip power grid and generating sign-off quality dynamic voltage drop waveforms for each instance in the design. It combines this effect with the coupling noise to accurately analyze clock jitter and critical path timing.
Cell-based Flow with True-SPICE Accuracy
SPICE is the ultimate authority in silicon-correlated accurate simulation. However, with the capacity and performance limitations of traditional SPICE simulators, it is impossible to simulate an entire SoC design. In addition, it is very time-consuming and error-prone for a designer to generate a SPICE netlist that contains the clock tree network or critical path that includes the coupling network, coupling drivers / receivers, and power / ground supply. Even with a SPICE netlist, traditional SPICE simulators are limited in their capacity and performance to simulate the network.
RedHawk-PSI delivers standard-cell capacity with a SPICE-accurate simulation of clock tree networks and critical paths, including all the nanometer and high-speed effects, such as crosstalk and dynamic voltage drop. RedHawk-PSI utilizes a true-SPICE simulator with proprietary BLSN (big linear, small non-linear) technology to accelerate the solving of networks that have an enormous number of linear elements, and a smaller number of non-linear elements.
RedHawk-PSI automatically generates SPICE netlist containing all the devices in the clock tree or critical path, including the parasitics in the routing, and potential aggressors coupled to the nodes in the path. Then it applies instance-specific Vdd/Vss waveforms to all power and ground pins of the gates in the path, and automatically runs distributed SPICE simulation using LSF and/or Sun Grid multiple machine processing for higher throughput. RedHawk-PSI reads in standard STA format files for clock tree and critical path analysis.
Ultimate Timing Sign-off Solution
For designs at 65nm and below nodes, the concurrent effects of power and signal integrity must be considered for timing signoff verification. This must be done using a dynamic analysis methodology with true-SPICE accuracy within a cell-based flow. With RedHawk-PSI, designers are able to quickly and accurately analyze clock jitter and critical path timing for the ultimate timing signoff of their nanometer design.