RedHawk

RedHawk-NX

RedHawk-NX is a next generation full-chip power integrity solution architected to meet the capacity and performance requirements in advanced designs. It provides an integrated environment for analyzing Power, Noise and Reliability issues in SoC designs.

RedHawk-NX performs transient simulation with pico-second resolution to accurately analyze the effects of simultaneous switching noise coming from core logic, memory, macro, and I/O. It considers the on-chip and off-chip capacitance elements such as device capacitance (intentional and intrinsic), load, power-grid, and well capacitance, as well as package and board parasitics. It integrates transistor-level SPICE modeling, inductance extraction of the on-die power grid, and package and system level parasitics for analysis of high performance SoCs. RedHawk-NX can be used across the implementation cycle starting from early-stage design analysis to pre-tapeout power sign-off and post silicon debug. It is silicon-proven with thousands of successful tape-outs by leading semiconductor and fabless semiconductor companies.

Key Benefits

Provides spice accurate flat transient simulation results at SoC level through power-noise aware modeling of standard cells, memories and IPs
Faster turn around time using high performance multi-CPU engine and MPR (Mesh Pattern Recognition) technology
Early prototyping and analysis for package selection and re-design risk mitigation late in the design cycle
Unified analysis and debugging environment, including integrated root cause identification technology, reduces debug cycle time
Chip-Package-Board co-design analysis for faster system-level power integrity closure

Key Functionalities

High capacity and performance through NX technology
Accurate extraction engine for the latest technology nodes
Advanced Vectorless and VCD analysis
Spice characterization of standard cells
Memory and macro modeling
Design optimization with “what-if” and FAO
Early design prototyping and analysis
Unified analysis and debugging environment
RedHawk Explorer (RHE) for root cause identification

High Capacity and Performance through NX Technology

The advanced technologies in RedHawk-NX include the industry’s first hierarchical dynamic power analysis, proprietary mesh pattern recognition and reuse, multi-core support, and efficient memory management, enabling designers to analyze the most complex designs with sign-off accuracy.

RedHawk-NX’s hierarchical dynamic technology uses custom macro models (CMM) to abstract the analysis results within the IP. Analysis using CMM delivers 30-50% reduction in runtime, peak memory usage, and disk space consumption, compared to a full flat analysis, while maintaining accuracy of results within 2-3%. The capacity improvements using CMM is greater when sub-blocks or macros/memory modules are instantiated multiple times in the design.

Figure 1: Hierarchical modeling of memories and IPs

RedHawk-NX also supports industry’s first hierarchical extraction technology, Mesh Pattern Recognition (MPR), which utilizes the regularity of patterns in the power grid network for data re-use and effective reduction of physical memory needs. The benefits are significant for stages of analysis that are most impacted by design size such as extraction and matrix solve, providing database 2-3X reduction in memory footprint.

RedHawk-NX employs a database technique that allows designers to trade off run-time performance with the physical memory size of their machine. Based on the available memory space, it automatically loads the database from cache, as needed for high-capacity, high-performance analysis and verification.

Additionally by using the multiple cores that are present in today’s computing systems, RedHawk-NX can parallelize computation tasks and reduce the run-times by as much as 2-3X compared to running on a single thread, especially for MTCMOS rush current analysis.

Accurate Extraction Engine for Advanced Technology Nodes

RedHawk-NX’s integrated high-performance full-chip extraction engine creates on-die power and ground grid RLC views by working on multiple power and ground domains simultaneously. It’s current-direction-aware extraction technology delivers accurate power EM analysis, resulting in least number of false EM violations. RedHawk-NX can handle advanced rules which consist of EM limit variation for different width, length, thickness and temperature, as well as blech-aware EM. RedHawk-NX extraction technology is certified to support TSMC’s iRCX for 65nm and 40nm technologies.

Advanced Vectorless and VCD Analysis Options

To address the challenges of generating vectors early in the design phase, RedHawk-NX provides Vectorless Dynamic engine for full-chip dynamic analysis. The Vectorless engine generates a cycle-by-cycle switching scenario honoring user specified constraints. It provides extended analysis coverage by considering various design weakness scenarios that can introduce power integrity issues. For example, RedHawk-NX assigns more weight to logically valid scenarios, such as highly localized simultaneous switching due to clock buffer clustering and increasing switching conditions in weak power grid regions. Designers can accurately analyze the impact of package parasitic, on-chip inductance, and decoupling capacitance on transient “hot spots”, without requiring VCD files or stimulus.

RedHawk-NX provides smart Vectorless techniques to model the power transients caused by sudden power steps such as system reset sequencing. The frequency-aware Vectorless option generates switching scenario that considers resonance frequency of chip-package-system. This can be used to study the package resonance impacts by creating the highest impedance state for the system. Also RedHawk-NX’s Vectorless scan technique supports ATPG-based power integrity analysis without requiring any vectors.

RedHawk-NX transient simulation supports both gate (toggle information for every gate) and RTL (toggle information for every state and primary I/O point) vectors in industry standard formats. When using RTL VCD, its “state propagation” engine will derive the toggle activity at the other logic points. RedHawk-NX’s “cycle selection” mode will scan through a VCD file and identify the relevant clock periods based on several criteria such as power consumption, power variation, potential impact on DvD, and frequency content.

SPICE Characterization of Standard Cells

Apache Power Library (APL) is used to characterize the electrical parameters for standard cells in the design. Every cell in the design is pre-characterized using SPICE simulation to model switching current waveforms and RC parasitic information for different input slew, output load, supply voltage, and operating states. RedHawk uses this model to simulate all power and ground domains simultaneously and the switching current drawn by each cell is updated at every time step based on the effective voltage seen by the cell.

Figure 2: APL current characterization as a function of voltage

All the necessary capacitive elements in the design including cell intrinsic capacitance, load capacitance, intentional decoupling capacitance, and well capacitance are included in the simulation along with their respective resistive components. A package and board model in either S-parameter or RLCK format is also considered during true-transient simulation. Its detailed linear representation of the non-linear elements makes SPICE accurate results possible in a full-chip level transient simulation. Typically, RedHawk-NX’s transient simulation voltage waveforms results are within 2% of SPICE and measured silicon.

Memory and Macro Modeling:

For memories and custom macros, RedHawk-NX uses the detailed GDS views for modeling the power grid. Current distribution inside the memory and macro can be modeled at various levels of accuracy. It can intelligently identify the regions of memory bit-cells and adjust the current distribution within the memory for higher degrees of accuracy.

Figure 3: RedHawk memory modeling

RedHawk-NX characterizes SPICE accurate current waveforms and capacitance data for memories and macros. In the absence of SPICE characterized data, RedHawk-NX can construct the current waveforms from the library power numbers. It can take the transistor-level SPICE characterized models for memories and IPs from the Totem platform through Custom Macro Models (CMM). Using this model, SoC designer can perform transistor-level analysis for memories and macros within the SoC design.

Design Optimization with “What-if” and FAO

From within the RedHawk-NX’s GUI, the designer can perform extensive "what-if" analysis for power-grid exploration and design tradeoffs assessments. The easy-to-use, layout-driven, incremental "what-if" capability, including incremental extraction, enables the designer to explore design fix scenarios with a rapid turn-around time. SoC designers can run "what-if" analysis to assess design tradeoffs, such as package RLC effects, as well as accurately determine the amount of decoupling capacitance to use and precisely where to insert the intentional capacitance. In addition, designers can explore different ways to reduce IR drop and EM violations by adding, deleting or editing power/ground pads, power straps, and vias/via arrays, and adding or deleting power gates in the design.

Once the full-chip transient “hot spots” are exposed, RedHawk-NX with optional Fix and optimize (FAO) feature optimizes decoupling capacitance by analyzing the full-chip intrinsic parasitic and computing the additional intentional decoupling capacitance required to reduce the peak IR drop. This enables designers to determine the amount of de-caps to use and precisely how to insert them near the "hot spots". Decap optimization can be accomplished early in the design stage to ensure that the location and the correct amount is allocated during the placement stage.

RedHawk-NX also provides information about de-cap cells that are not effective in suppressing the power noise generated on the die, thus assisting the designers to eliminate them and reducing their impact on leakage and yield.

RedHawk-NX with FAO can be used to re-design the power grid mesh either in local area (fixing) or over the whole chip (optimization) by specifying certain constraints. Without compromising the total voltage drop, it increases metal resources in the areas of dynamic "hot spots", while reducing the metal widths of the areas with low voltage drop to avoid over-designing. Its non-uniform grid optimization allows designers to specify constraints such as area, metal layers, and target drop. Since the optimization engine is tightly integrated with RedHawk-NX's proven dynamic analysis engine, the designers can feel confident with the accuracy of the optimized grid.

Figure 4: Design fixing using RedHawk-FAO

Early Prototyping and Analysis

RedHawk-NX allows power grid prototyping based on design specifications and technology information. It determines the on-die power grid design style and metal resource usage that are required to meet the design’s power delivery constraints. The designers can build an early design database in the RedHawk environment by using an extensive set of layout drawing commands, or read in partial design information. Initial floor plan data such as placement information for the blocks or definition of regions containing certain functional units, along with power consumption data for various blocks, macros, and regions, are used to perform early power analysis for the design. Average and transient current assignment can be done at region level and its distribution can be controlled by the user.

RedHawk-NX provides pad/bump placement guidance and identifies current congestion areas on the die. It also provides guidance for power-gate design and placement. An early prototype analysis can lead to the creation of early die models, Chip Power Model (CPM). For the package and board designers, CPM has several benefits, such as visibility into the required number of layers in a package, the needed pin count, and the routing and via placement challenges. Even with the availability of minimal data, RedHawk-NX provides intuitive and interactive capabilities, such as mesh creation, automatic via placement, pad, switch, and de-cap placement to model the early design.

Unified Analysis and Debugging Environment

RedHawk-NX provides a single unified environment for analysis and debugging of power, noise, and timing. Its layout based GUI provides designers with the flexibility and robustness required for easy-to-use yet comprehensive debugging capabilities.

Figure 5: RedHawk GUI

From within the RedHawk-NX environment, designers can access various views of their design, including layout view of the power density, instance power, and dynamic voltage drop. RedHawk also provides a number of waveform views such as total current/charge profile and instance-based VDD drop and VSS ground bounce. Its full-chip movie mode playback with instance-based voltages over time assists designers in gaining access to critical information required to analyze and debug their designs.

RedHawk Explorer

RedHawk Explorer (RHE) is an extension to RedHawk which helps the designer in locating, isolating, understanding, and resolving various power integrity issues in SoC designs. RHE is tightly integrated with RedHawk and provides very powerful cross-probing capabilities with the RedHawk GUI.

Figure 6: RedHawk Explorer summary view

RedHawk Explorer can perform data integrity analysis, design weakness exploration, and root cause identification for different hot-spots in the design. It also generates a concise summary for various analysis results.

RedHawk Explorer sanitizes the user input data and alerts the designer if there are any data integrity issues. It highlights the regions in the design which are affected with various issues including library/design input data coverage and missing-vias and shorts in the layout. It generates detailed reports and provides easy navigation options for the designers to browse through the reports. It also checks analysis settings used by the designer and offers recommendations if there are any settings which are out of range.

Figure 7: Data integrity analysis using RedHawk Explorer

RedHawk Explorer performs qualitative design weakness check of parameters that can cause power integrity issues. For example, it checks pad placement quality, power/ground weakness, simultaneous switching, etc. and highlights regions with design weaknesses. It provides interactive cross probing with RedHawk GUI and allows the designer to control the thresholds in various qualitative checks.

Minimum Resistance Path Tracing in RHE highlights the electrically shortest route from Power/Ground voltage sources to any instance in the design. The generated resistance report shows the minimum resistance path highlighting the bottleneck segments.

Figure 8: Connectivity tracing using RedHawk Explorer

During root cause identification, RHE analyzes various voltage drop/EM hot spots in the design and identifies their root cause. It back-traces the data integrity issues and design weaknesses, and highlights the problems in the “hot spot” region/instance.

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