- PowerArtistRTL Power Reduction, Analysis, Debug, and RPM Generation
- RedHawkSoC Dynamic Power, Advanced Low Power, Reliability, and Chip-Package Co-design
- TotemAnalog/Mixed-Signal Dynamic Power, Substrate Noise, EM, and ESD
- SentinelChip-Package-System Power/Signal Integrity, IO-SSO, Thermal, and EMI
- ResourcesTechnical Papers and Presentations, Contributed Articles and Conference Papers, Webinars and Videos
RedHawk-ALP is a full-chip and block-level true transient dynamic power integrity solution for analysis and optimization of advanced low power and leakage control designs. RedHawk-ALP provides extensive design analysis capabilities, while considering the complexities associated with various power-saving features such as:
- Multiple Vth (threshold voltage) circuit styles
- Multiple voltage islands with multiple voltage cells
- Power-gating / MTCMOS (multi-threshold CMOS) switches with retention flops for off-state leakage control
- Switched memories
- On-chip LDO (low drop-out) voltage regulators
- Substrate back-biasing
RedHawk-ALP performs full-chip and block-level true transient (time-point by time-point) dynamic analysis, as well as static (average power) analysis by accurately modeling the presence of one or more of the above power saving modes. RedHawk-ALP expands Apache’s silicon proven full-chip dynamic power solution to deliver the most accurate power analysis and design optimization for low power SoCs.
- Full-chip capacity and overnight performance for milli-seconds of simulation
- Spice accurate non-linear modeling of MTCMOS switches, LDO, and back-biasing circuits
- Transient simulation with transistor-level waveform accuracy
- Power switch optimizations, including size, location, and number, for optimal performance
- Reduced leakage by eliminating ineffective switches and decaps
- Mixed-mode analysis of ramp-up impact on timing
- Various visualization tools, including full-chip movie playback of instance-based voltages over time
Low Power Design Challenges
Advancements in silicon process technology offer smaller transistors and higher packaging density, but suffer from increased power consumption, especially for high-speed, high-data-rate systems. For the next generation graphics chips, more than 50% of total power is estimated to come from leakage. As for wireless devices such as cell phones, one of the key design requirements is to extend the life of the battery. To meet this requirement, designers need to minimize the power consumed during standby mode to no more than 5% of total operational power. Moving forward, the competitiveness of a product will highly depend on its ability to control leakage.
In order to lower power consumption and control leakage currents, all designs at the 65nm process node and below utilize some form of low power and/or leakage control techniques, as leakage will dominate the overall power consumption.
Power-gating, or MTCMOS switching, is rapidly being adopted as a method for controlling off-state standby leakage in high-performance, low-power designs. The concept of power-gating is to disconnect the devices from their power or ground sources when off, thus reducing the leakage current flow by creating a break in the power or ground networks. This is usually accomplished through the addition of one or more “switch” circuits to the power or ground network that connect the block or chip level power or ground networks to the external power and ground networks, respectively.
Figure 1: MTCMOS header and footer switches
Accurate verification of power-gated designs requires full-chip power-up (ramp-up) simulation and mixed-mode transient analysis, where some parts of the design are in the on-state, while different blocks are in power-up state.
RedHawk-ALP delivers Spice-accurate non-linear modeling of MTCMOS switches, full-chip capacity and performance, and true-transient simulation for accurate analysis of designs utilizing power-gating techniques.
Performing a ramp-up (sleep to active) analysis of power-gated blocks within a design requires the ability to run long simulation – micro- to milli-seconds – within a reasonable time. RedHawk-ALP delivers full-chip capacity, allowing designers to simulate billions of transistors for hundreds of thousands of cycles overnight. This enables designers to accurately analyze the ramp-up performance, such as peak current drawn by the block and the time it takes to power-up the entire block.
Proper representation of the behavior of MTCMOS switches during ramp-up requires non-linear modeling and transient analysis. RedHawk-ALP generates non-linear MTCMOS switch models, as well as instance models to be used during ramp-up analysis. These models are simulated using a transient analysis engine for time-point by time-point verification of the circuit behavior, thus delivering transistor-level waveform accuracy.
RedHawk-ALP enables designers to analyze the ramp-up process in their designs. It uses its proven full-chip transient analysis capabilities to deliver, with Spice-like accuracy, current and voltage waveforms as seen in the design during the power-up process. To accurately capture the power-up process, RedHawk-ALP models a power gate as a voltage-dependent element whose parameters change as the voltage across the power gate changes as it powers up from the sleep state.
Figure 2: Ramp-up voltage and current correlation
During ramp-up, the current surge of a block powering up can impact the voltage drop of surrounding cells, which in turn can impact the timing of those cells. RedHawk-ALP provides full-chip spatial and temporal mixed-mode analysis, capturing the interaction of blocks within a design running various modes (always on, power-up, standby, off), and as each block transitions from one state to another.
Figure 3: Mixed-mode analysis – impact of always-on logic on power-up block
Power Switched Memories
The off-state standby leakage power saving requirements for low-power designs often leads to the usage of Power Switched memories, where the power gating structure is an integral part of the memory IP. RedHawk-ALP with its SPICE-based modeling enables the designers to accurately analyze the behavior of Power Switched RAM, not only during functional mode but also during the ramp-up process in the full chip context. Its SoC capacity enables analysis of coupling noise during power-up with the impact consideration of neighboring logic, where timing is critical.
Leakage Optimization and Switch Timing Strategy
RedHawk-ALP enables the designers to explore and optimize their low power design by providing various visualization tools and optimization capabilities. Tools such as current and voltage viewers, the movie playback of instance based voltage variation over time, and automatic checks and reports, allow designers to easily control the rush current, anticipate the ramp-up time, validate the leakage saving, and analyze the risk of crowbar current.
Figure 4: Switch optimization and power-up timing analysis
RedHawk-ALP with FAO allows designers to accurately determine the size, number, location, and ramp-up time of power gating switches for optimal performance. It also provides the ability to remove ineffective decaps and switches, thus reducing excessive leakage current caused by devices that do not contribute to the overall power integrity of the chip.
One of the key low power design techniques for controlling the power vs. performance trade-off is the use of multiple Vdd and Vss cells. These cells that are typically found in level-shifters, memories, and retention flip-flops, support multiple Vdd and Vss levels and act as a bridge between multiple voltage domains.
RedHawk-ALP handles instance-based multiple-Vdd/Vss cells, allowing designers to concurrently analyze the current profile and power distribution for each of the voltage domains.
Figure 5: Multi-voltage island and multi-vdd/vss example
Full-chip Clock-gating Analysis
Clock-gating is one of the most common techniques used for reducing switching power in nanometer SoC designs. An accurate analysis of dynamic power and voltage drop of a clock-gated design requires a realistic clocking scheme. RedHawk-ALP uses RTL-VCD and Apache’s patented Vectorless Dynamic algorithm with state-propagation to identify realistic clock tree analysis switching scenarios.
Figure 6: Clock-gating analysis
Gating part of the clock network reduces the switching activity, thus reducing the overall power consumption of the chip. However, as the gated clock is turned back on, the current drawn by this clock network impacts the dynamic voltage drop on the already “on” networks. RedHawk-ALP delivers full-chip analysis of clock-gated designs, considering all interactions between various blocks with different clocking schemes and any transitions between any of the schemes.
On-chip LDO (low drop-out) voltage regulators
The Low Dropout Regulator (LDO) is a common low-noise power source. It is popular with battery-powered SoCs due to its low dropout voltage and low quiescent current. Driven by cost, integration, and numerous multi-voltage islands and/or back-biasing techniques, LDOs are being instantiated more and more on a chip.
Figure 7: LDO circuit example
RedHawk-ALP allows designers to validate its maximum load current and minimum dropout voltage depending on the SoC switching activity in either functional or test modes. It also provides the capabilities to analyze the output-capacitor’s effective series resistance (ESR) and guides the designers in capacitance selection, placement and routing. In addition, RedHawk-ALP handles on-board output capacitance by including the package and board models. RedHawk-ALP provides SPICE accurate LDO models and performs Dynamic Voltage Drop analysis of the SoC with the consideration of LDO(s) behavior as the power source, instead of traditional ideal sources.