- PowerArtistRTL Power Reduction, Analysis, Debug, and RPM Generation
- RedHawkSoC Dynamic Power, Advanced Low Power, Reliability, and Chip-Package Co-design
- TotemAnalog/Mixed-Signal Dynamic Power, Substrate Noise, EM, and ESD
- SentinelChip-Package-System Power/Signal Integrity, IO-SSO, Thermal, and EMI
- ResourcesTechnical Papers and Presentations, Contributed Articles and Conference Papers, Webinars and Videos
RedHawk-3DX is the fourth generation full-chip power integrity and sign-off solution re-architected to meet the accuracy and capacity demands of sub-20nm process technology, and in conjunction with RedHawk-MDO, enables the simulation of multi-die / 3D-IC designs. For more than a decade, RedHawk has been the industry standard for solving critical power integrity issues and is used as a sign-off solution by world’s top semiconductor companies. The latest generation of RedHawk supports sub-20nm extraction and electromigration (EM) modeling, innovative hierarchical analysis technologies, and enhanced logic handling for greater sign-off coverage.
RedHawk performs transient simulation with pico-second resolution to accurately analyze the effects of simultaneous switching noise coming from core logic, memory, macro, and I/O. It considers the on-chip and off-chip capacitance elements such as device capacitance (intentional and intrinsic), load, power-grid, and well capacitance, as well as package and board parasitics. It integrates transistor-level SPICE modeling, inductance extraction of the on-die power grid, and package and system level parasitics for analysis of high performance SoCs. RedHawk can be used across the implementation cycle starting from early-stage design analysis to pre-tapeout power sign-off and post silicon debug. It is silicon-proven with thousands of successful tape-outs by leading semiconductor and fabless semiconductor companies.
- Hierarchical extraction and simulation using ERV (Extraction Reuse View) to handle billion+ gate, multi-core designs with sign-off accuracy
- Fast turn-around time using high performance multi-CPU engine and MPR (Mesh Pattern Recognition) technology
- Sub-20nm support for power and signal EM verification
- Accurate modeling and analysis of advanced low power design techniques including LDO (low-drop-out) on-chip voltage regulator
- Early prototyping and analysis for package selection and re-design risk mitigation late in the design cycle
- Unified analysis and debugging environment, including integrated root cause identification technology, reduces debug cycle time
- Chip-Package-Board co-design analysis for faster system-level power integrity closure
- Multi-die / 3D-IC design modeling and analysis including silicon interposer and TSV (through silicon via)
- Highest capacity and performance with ERV and MPR technologies
- Accurate extraction engine for the latest technology nodes
- Advanced Vectorless and VCD analysis with enhanced logic handling for RTL to Gates methodology
- Spice characterization of standard cells
- Memory and macro modeling
- Design optimization with “what-if” and FAO
- Early design prototyping and analysis
- Multi-pane GUI for multi-die/3D-IC design analysis and debug
- RedHawk Explorer (RHE) for root cause identification
High Capacity and Performance
Unlike timing or cross-talk analysis, power noise analysis is a global or “full-chip” problem and cannot be solved by partitioning the design. Because of shared PDN (power delivery network) routing on the chip or in the package, power noise or current flow in one part of the design may significantly affect another part of the design.
The advanced technologies in RedHawk-3DX include ERV (Extraction Reuse View), an innovative hierarchical extraction and modeling technologies that delivers full-chip capacity and performance without sacrificing the sign-off accuracy. This combined with re-architected dynamic simulation engine for dynamic voltage drop and ramp-up analyses result in up to 40% overall performance improvements over its previous generation.
RedHawk-3DX’s unique ERV technology enables designers to perform hierarchical chip-level simulation using a model representation of all or most of their blocks and IPs. These hierarchical models capture its electrical signature and PDN parasitics in a compact format to help predict its’ impact on full-chip design and IC package. ERV delivers up to 50% simulation node reduction, enabling billion+ gate design analysis and is particularly effective in multi-core designs, which are commonly found in today’s ICs.
Figure 1: Design Size using Flat vs. ERV
RedHawk-3DX also employs MPR (Mesh Pattern Recognition) technology which utilizes the regularity of patterns in the power grid network to effectively reduce physical memory usage and database technique that allows designers to trade off run-time performance with the physical memory size of their machine. Additionally by using the multiple cores that are present in today’s computing systems, RedHawk-3DX can parallelize computation tasks and reduce the run-times by as much as 2-3X compared to running on a single thread.
Accurate Extraction Engine for Advanced Technology Nodes
As supply voltages decrease, designers are faced with managing significantly reduced noise margin. Accurate dynamic voltage drop analysis is critical for ensuring that the next-generation ICs meet the required performance targets. RedHawk addresses accuracy concerns with its well-proven technologies such as APL (Apache Power Library), on-chip inductance modeling, and support for multi-port broadband S-parameter package/PCB netlists.
RedHawk-3DX advances the focus on accuracy with sub-20nm extraction and EM (electromigration) modeling capabilities. Its’ current-direction-aware, metal-topology-aware, and temperature-aware extraction technologies deliver accurate power and signal EM analysis that meets the complex and stringent foundry design rules. RedHawk’s extraction technology is certified to support TSMC’s iRCX for 65nm, 40nm, and 28nm technologies.
Figure 2: Sub-20nm Electromigration Rules and Issues
Advanced Vectorless and VCD Analysis Options
RedHawk-3DX improves accuracy and coverage of dynamic power analysis by delivering new event- and state-propagation technologies with vector-based and VectorLess™ modes. This enhanced logic capabilities enable designers to gain more comprehensive understanding of the power behavior scenarios.
RedHawk-3DX’s fast event-propagation engine enables an “RTL-to-Gates” methodology by supporting the use of RTL (register transfer language)-level VCD so that the designers can perform simulations without requiring the availability of hard to obtain gate-level vectors. By leveraging PowerArtist™ and RPM™ (RTL Power Model), millions of cycle RTL stimulus can be pruned to few power critical (peak power or peak di/dt) cycles which then can be used by RedHawk-3DX logic propagation engine to perform cycle accurate dynamic voltage drop analysis.
Figure 3: RTL-to-Gate Power Methodology
Figure 4: RTL VCD vs. Gate VCD Correlation
To address the challenges of RTL or gate-level vectors availability early in the design phase, RedHawk since its first generation version, has been providing VectorLess Dynamic engine for full-chip dynamic analysis.
RedHawk-3DX introduces new VectorLess state-propagation engine which tackles the problem of “toggle die-down” associated with most activity-based propagation engines. It uses toggle activities at the primary I/Os, registers, etc. as input to the engine, which in turn uses its proprietary “smart detection and pruning” techniques to eliminate the traditional problem of underestimating the toggle rates in cone of logic.
In addition, RedHawk’s frequency-aware VectorLess capability generates switching scenario that considers resonance frequency of chip-package-system that can be used to study the package resonance impacts by creating the highest impedance state for the system. Its VectorLess scan technique supports ATPG-based power integrity analysis without requiring any vectors.
RedHawk-3DX also supports a flexible mixed-excitation mode where some blocks use RTL or gate-level VCDs while the rest of the design uses VectorLess to derive the chip’s switching activity. This allows designers to perform accurate full-chip dynamic power analysis by mixing simulation engines based on the availability of the stimulus.
Figure 5: Advanced Mixed VCD and VectorLess Analysis
SPICE Characterization of Standard Cells
Apache Power Library (APL) is used to characterize the electrical parameters for standard cells in the design. Every cell in the design is pre-characterized using SPICE simulation to model switching current waveforms and RC parasitic information for different input slew, output load, supply voltage, and operating states. RedHawk uses this model to simulate all power and ground domains simultaneously and the switching current drawn by each cell is updated at every time step based on the effective voltage seen by the cell.
Figure 6: APL current characterization as a function of voltage
All the necessary capacitive elements in the design including cell intrinsic capacitance, load capacitance, intentional decoupling capacitance, and well capacitance are included in the simulation along with their respective resistive components. A package and board model in either S-parameter or RLCK format is also considered during true-transient simulation. Its detailed linear representation of the non-linear elements makes SPICE accurate results possible in a full-chip level transient simulation. Typically, RedHawk’s transient simulation voltage waveforms results are within 2% of SPICE and measured silicon.
Memory and Macro Modeling
For memories and custom macros, RedHawk-3DX uses detailed GDS views for modeling the power grid. Current distribution inside the memory and macro can be modeled at various levels of accuracy. It can intelligently identify the regions of memory bit-cells and adjust the current distribution within the memory for higher degrees of accuracy.
Figure 7: RedHawk memory modeling
RedHawk-3DX characterizes SPICE accurate current waveforms and capacitance data for memories and macros. In the absence of SPICE characterized data, RedHawk can construct the current waveforms from the library power numbers. It can take the transistor-level SPICE characterized models for memories and IPs from the Totem™ platform through Custom Macro Models (CMM). Using this model, SoC designer can perform transistor-level analysis for memories and macros within the SoC design.
Design Optimization with “What-if” and FAO
From within the RedHawk-3DX’s GUI, the designer can perform extensive "what-if" analysis for power-grid exploration and design tradeoffs assessments. The easy-to-use, layout-driven, incremental "what-if" capability, including incremental extraction, enables the designer to explore design fix scenarios with a rapid turn-around time. SoC designers can run "what-if" analysis to assess design tradeoffs, such as package RLC effects, as well as accurately determine the amount of decoupling capacitance to use and precisely where to insert the intentional capacitance. In addition, designers can explore different ways to reduce IR drop and EM violations by adding, deleting or editing power/ground pads, power straps, and vias/via arrays, and adding or deleting power gates in the design.
Once the full-chip transient “hot spots” are exposed, RedHawk-3DX with optional Fix and optimize (FAO) feature optimizes decoupling capacitance by analyzing the full-chip intrinsic parasitic and computing the additional intentional decoupling capacitance required to reduce the peak IR drop. This enables designers to determine the amount of de-caps to use and precisely how to insert them near the "hot spots". RedHawk-3DX also provides information about de-cap cells that are not effective in suppressing the power noise generated on the die, thus assisting the designers to eliminate them and reducing their impact on leakage and yield.
RedHawk-3DX with FAO can be used to re-design the power grid mesh either in local area (fixing) or over the whole chip (optimization) by specifying certain constraints. Without compromising the total voltage drop, it increases metal resources in the areas of dynamic "hot spots", while reducing the metal widths of the areas with low voltage drop to avoid over-designing. Its non-uniform grid optimization allows designers to specify constraints such as area, metal layers, and target drop. Since the optimization engine is tightly integrated with RedHawk's proven dynamic analysis engine, the designers can feel confident with the accuracy of the optimized grid.
Figure 8: Design fixing using RedHawk-FAO
Early Prototyping and Analysis
RedHawk-3DX allows power grid prototyping based on design specifications and technology information. It determines the on-die power grid design style and metal resource usage that are required to meet the design’s power delivery constraints. The designers can build an early design database in the RedHawk environment by using an extensive set of layout drawing commands, or read in partial design information. Initial floor plan data such as placement information for the blocks or definition of regions containing certain functional units, along with power consumption data for various blocks, macros, and regions, are used to perform early power analysis for the design. Average and transient current assignment can be done at region level and its distribution can be controlled by the user.
RedHawk-3DX provides pad/bump placement guidance and identifies current congestion areas on the die. It also provides guidance for power-gate design and placement. An early prototype analysis can lead to the creation of early die models, Chip Power Model (CPM™). For the package and board designers, CPM has several benefits, such as visibility into the required number of layers in a package, the needed pin count, and the routing and via placement challenges. Even with the availability of minimal data, RedHawk provides intuitive and interactive capabilities, such as mesh creation, automatic via placement, pad, switch, and de-cap placement to model the early design.
Multi-die / 3D-IC Design Analysis and Debug
RedHawk-3DX along with RedHawk-MDO (multi-die option) enables modeling, simulation and debug of multi-die or 3D-IC designs, including silicon interposer and TSVs. It offers designers the ability to perform concurrent or model-based analysis. In a concurrent mode, every component of the stacked-die design, including silicon interposer and TSV are concurrently simulated with full-layout detail. For dice without layout information, the model-based approach will use CPM to capture their electrical signatures (current and parasitics).
As 3D-ICs stack multiple dice, each die’s power density has direct impact on the other die’s thermal profile. RedHawk-3DX effectively analyzes the power-thermal coupling effects of a multi-die design.
RedHawk-3DX provides a new multi-pane, multi-tab GUI allowing designers to view the results of multiple dice simultaneously for analysis and debugging of power, noise, and timing. The layout based GUI provides designers with the flexibility and robustness required for easy-to-use yet comprehensive debugging capabilities.
Figure 9: 3D-IC Voltage Drop using Multi-Pane GUI
From within the RedHawk-3DX environment, designers can also simultaneously access various views of a single IC design, including layout view of the power density, instance power, and dynamic voltage drop. RedHawk also provides a number of waveform views such as total current/charge profile and instance-based VDD drop and VSS ground bounce.
RedHawk Explorer (RHE) is an extension to RedHawk which helps the designer in locating, isolating, understanding, and resolving various power integrity issues in SoC designs. RHE is tightly integrated with RedHawk and provides very powerful cross-probing capabilities with the RedHawk GUI.
Figure 10: RedHawk Explorer summary view
RedHawk Explorer can perform data integrity analysis, design weakness exploration, and root cause identification for different hot-spots in the design. It also generates a concise summary for various analysis results.
RedHawk Explorer sanitizes the user input data and alerts the designer if there are any data integrity issues. It highlights the regions in the design which are affected with various issues including library/design input data coverage and missing-vias and shorts in the layout. It generates detailed reports and provides easy navigation options for the designers to browse through the reports. It also checks analysis settings used by the designer and offers recommendations if there are any settings which are out of range.
Figure 11: Data integrity analysis using RedHawk Explorer
RedHawk Explorer performs qualitative design weakness check of parameters that can cause power integrity issues. For example, it checks pad placement quality, power/ground weakness, simultaneous switching, etc. and highlights regions with design weaknesses. It provides interactive cross probing with RedHawk GUI and allows the designer to control the thresholds in various qualitative checks.
Minimum Resistance Path Tracing in RHE highlights the electrically shortest route from Power/Ground voltage sources to any instance in the design. The generated resistance report shows the minimum resistance path highlighting the bottleneck segments.
Figure 12: Connectivity tracing using RedHawk Explorer
During root cause identification, RHE analyzes various voltage drop/EM hot spots in the design and identifies their root cause. It back-traces the data integrity issues and design weaknesses, and highlights the problems in the “hot spot” region/instance.