RedHawk

RedHawk is the industry-standard next-generation dynamic power integrity solution from Apache with the capacity to handle designs over five hundred million gates, while maintaining sign-off accuracy. It accurately analyzes the effects of simultaneous switching noise (core, memory, I/O), decoupling capacitance (intentional and intrinsic), and on-chip / off-chip (package) inductance.

RedHawk allows designers to explore and identify physical design weaknesses (RHE), automatically repair the supply noise (FAO) source, analyze the impact of dynamic voltage drop on timing and jitter (PSI), verify power and signal EM (SEM), validate ESD protection robustness (PathFinder™), and provide a power delivery network (PDN) model profile for system-level analysis (CPM™).

RedHawk (ALP) performs rush-current and ramp-up analysis, multi-mode verification, and intelligent switch optimization for ultra-low-power design techniques including multiple voltage islands, MTCMOS (power-gating), VTCMOS (substrate back-biasing), switched memories, and on-chip LDO (low drop-out) voltage regulators. RedHawk enables designers to meet the power budget, power delivery integrity, and power-induced noise immunity targets for their IC.

	A next generation full-chip dynamic power integrity solution with the capacity and performance required for advanced designs.
	A full-chip and block-level dynamic power integrity solution for analysis and optimization of advanced low power designs.
	A full-chip clock network integrity (jitter) and critical path timing signoff solution for high-performance nanometer designs.
	A full-chip signal EM solution with accurate and detailed Average, RMS, and peak EM violation analysis.
	A compact and SPICE-accurate model of the full-chip power delivery network behavior.
	The industry's first comprehensive layout-based electro-static discharge (ESD) integrity solution.
	Die modeling of the noise source, 3D full-wave electromagnetic simulation, and tools to pinpoint the origin of noise within the chip.