RedHawk

RedHawk is a next generation dynamic power integrity solution with the capacity to handle designs of more than five hundred million gates, while maintaining sign-off accuracy. It accurately analyzes the effects of simultaneous switching noise (core, memory, I/O), decoupling capacitance (intentional and intrinsic), and on-chip and off-chip (package) inductance.

RedHawk enables designers to explore and identify physical design weaknesses (RHE), automatically repair source of supply noise (FAO), analyze the impact of dynamic voltage drop on timing and jitter (PSI), verify power and signal EM (SEM), validate ESD protection robustness (PathFinder), and provide a model of the chip power delivery network profile for system-level analysis (CPM).

RedHawk for low power (ALP) provides analysis and optimization of ultra low power design techniques including those used in 65/45/32nm designs such as multiple voltage islands, MTCMOS (power-gating), VTCMOS (substrate back-biasing), switched memories, and on-chip LDO (low drop-out) voltage regulators. It enables designers to perform rush current and ramp-up analysis and full-chip multi-mode verification, as well as intelligent switch optimization for further leakage improvements.

	A next generation full-chip power integrity solution with the capacity and performance required for advanced designs.
	A full-chip and block-level dynamic power integrity solution for analysis and optimization of advanced low power designs.
	A full-chip clock network integrity (jitter) and critical path timing signoff solution for high-performance nanometer designs.
	A full-chip signal EM solution with accurate and detailed Average, RMS, and peak EM violation analysis.
	A compact and SPICE-accurate model of the full-chip power delivery network.
	The industry's first comprehensive electro-static discharge (ESD) integrity solution.
	Consists of die model representing noise source, 3D full-wave electromagnetic simulation, and tools to pinpoint the origin of noise within the chip.