- PowerArtistRTL Power Reduction, Analysis, Debug, and RPM Generation
- RedHawkSoC Dynamic Power, Advanced Low Power, Reliability, and Chip-Package Co-design
- TotemAnalog/Mixed-Signal Dynamic Power, Substrate Noise, EM, and ESD
- SentinelChip-Package-System Power/Signal Integrity, IO-SSO, Thermal, and EMI
- ResourcesTechnical Papers and Presentations, Contributed Articles and Conference Papers, Webinars and Videos
Apache Customers Speak About the Benefits of PowerArtist
PowerArtist-XP is a complete RTL design-for-power platform with fully-integrated advanced analysis and automatic reduction. Utilizing a unique Analyze-Visualize-Reduce framework, PowerArtist-XP delivers maximum power savings for complex SoCs and IPs with a tight control over the design impact and downstream flow.
With a comprehensive set of power reduction techniques and a range of visual debug diagnostics, PowerArtist-XP is the low power design tool for RTL engineers. With PowerArtist-XP, they can quickly identify where power is being consumed, what it takes to reduce it, and control changes through a powerful user-friendly graphical cockpit, PowerCanvas. Depending on the reduction technique, it can automatically rewrite power-optimized RTL, output synthesis constraints, or guide the user through manual RTL rewrite.
The RTL changes preserve the original RTL formatting by making only precise, surgical changes to the code. With full-chip capacity, PowerArtist-XP runs multi-million gate-equivalent RTL in a matter of hours. PowerArtist-XP integrates with standard simulation, synthesis and formal verification flows.
- Achieves predictable single-pass power savings with production-proven RTL power analysis
- Maximizes power savings with clock, memory and datapath power reduction techniques
- Allows control of automatic power-efficient RTL generation for trade-off of power vs. other application-specific design constraints
- Guides synthesis clock gating for higher power savings and better skew control
- Delivers rapid power debug with a powerful yet intuitive graphical cockpit and user-programmable interface based on the Open Access database (OADB)
- Runs million gate-equivalent RTL in minutes with full-chip capacity
- High accuracy, capacity and performance RTL and gate-level power analysis
- Comprehensive power visualization and debug environment
- Automatic analysis-driven RTL power reduction techniques for clocks, memory, and datapath
- Power reduction browser with filter and sort capabilities
- Peak power and power vs. time analysis
- Design activity (vector) analysis
- OpenAccess database (OADB) API for customization and power regressions
- Power prototyping with ‘what-if’ analysis for power gating and voltage islands
- Accurate modeling of downstream optimizations for clock gating, multi-Vt
Production-proven Full-chip RTL Power Analysis
PowerArtist-XP offers the performance and breadth of algorithms needed to handle true full-chip RTL power analysis, even for multi-million gate designs. Fast yet accurate and comprehensive power analysis allows designers to pinpoint power problems early in the design flow. Patented RTL algorithms, proven on multi-million gate designs, provide an order of magnitude performance advantage over gate-level power analysis. PowerArtist-XP is able to efficiently analyze designs with multiple power supplies, mixed Verilog-Verilog2001-VHDL descriptions and embedded IP models.
PowerArtist-XP also works at the gate level, where it can be used both for post-synthesis, as well as post-layout power analysis with full SPEF backannotation.
PowerArtist-XP provides a powerful debug environment to analyze, display and help the user monitor power for the whole chip and each individual module. This analysis and debug cockpit features hierarchy, source code, schematic, and waveform viewers, as well as a database query and search engine.
Figure 1: PowerArtist-XP power analysis and debug environment
Automatic Analysis-driven RTL Power Reduction
In PowerArtist-XP, reduction is driven by the industry standard RTL power analysis technology. In use by over a 100 customers, the timing-aware RTL power analysis algorithms provide early access to power with proven correlation to gate-level power. This unique capability provides predictable power reduction and eliminates unnecessary iterations between RTL, gate netlist and physical netlist. Power reduction choices are quickly evaluated, up-front at RTL before synthesis, for various trade-off conditions. As a result, designers are able to achieve maximum power reduction with minimum RTL edits by focusing on the highest power saving opportunities. The sensitivity of a medical battery-operated device to area and leakage overhead can be significantly higher than an enterprise server for which performance is key. PowerArtist-XP provides the flexibility and the analysis to help designers make intelligent decisions that maximize power savings within the constraints to which their design application limits them.
Figure 2: PowerArtist-XP’s analysis-driven reduction enables intelligent design decisions – for maximum power savings, with minimum design impact
Power Reduction Browser with Filter and Sort Capabilities
PowerArtist-XP’s eXpert Power Reduction Technology (XPRT) is the comprehensive set of power reduction techniques delivering significant power savings. XPRT targets power reduction opportunities in clock, memory and datapath sections that are complementary to synthesis. It has a wide range of clock power reduction techniques from combinational to sequential clock gating that apply at the register and block level. It generates synthesis constraints to prevent insertion of those clock gates that can increase power consumption resulting in higher power savings. The constraints can also be used to eliminate a large number of clock gates that dp not save significant amount of power resulting in better clock skew control and less routing congestion. Memory power reduction techniques include memory gating and memory splitting. Datapath power reduction techniques eliminate power due to wasteful activity in deep cones of logic. It also helps locate power bugs that waste significant power in a functionally correct design. XPRT automatically generates power-efficient RTL and makes precise edits to preserve the original formatting.
Figure 3: PowerArtist-XP graphical cockpit drives power reduction
Peak Power and Power vs. Time Analysis
While average power is an important measure of the power consumption for package selection, battery life and cooling requirements, understanding mode-dependent and time varying power is a critical component of an effective SoC power strategy. Mode-based power allows user to separate power consumption by functional modes (e.g. active, standby, idle, sleep, scan, reset) of a chip and hence enables power debug. PowerArtist-XP allows user to define modes of operation and subsequently monitors each mode and its related power consumption. Time-based power at RTL enables power profiling at user-defined time intervals down to the logic simulation resolution. By providing visualization of where peak power is consumed, PowerArtist-XP addresses issues such as power bus sizing, electromigration analysis and power supply requirements prior to synthesis.
Figure 4: PowerArtist-XP power vs. time analysis
Design Activity (Vector) Analysis
Commercial code coverage and testbench design tools offer very little support for power concerns. As a result, most designers have difficulty understanding whether or not their vectors truly reflect their design’s power behavior. PowerArtist-XP vector analysis capability fills the gap, enabling designers to visualize activity for an entire test suite, for any combination of modules in the design, quickly identifying coverage problems and unexercised power modes. Throughout the design process, vector analysis can be used to visualize the activity in multiple hierarchical blocks to make sure the test suite covers the high power modes of operation, and selects small, power intensive time slices for detailed power verification. Using the vector analysis capability, designers can easily identify vector sets that do not have adequate activity to perform meaningful power analysis. Vector analysis can also identify vectors that may cause di/dt or electromigration issues, and aid designers in selecting critical vector sets for more detailed analysis.
Figure 5: PowerArtist-XP vector analysis
OpenAccess Database (OADB) API
PowerArtist-XP utilizes Si2’s OpenAccess standard database and supports OpenAccess API for database searches. Use of OpenAccess and OADB scripts enables designers to perform customized activity and power-related queries quickly and easily. Designers can build power regressions to track the power-efficiency of their designs and locate power-erratic design changes between various RTL versions. The API access can also be used for interoperability with other third party tools for low-power design.
Figure 6: OADB API enables customer interactive queries – also possible in batch mode
‘What-if’ Power Prototyping
PowerArtist-XP enables the user to predict the effects at global SOC-level as well as downstream fine-grained power reduction techniques such as power gating (power shutoff, PSO), voltage islands (multiple supply voltages, MSV), clock gating, and multi-Vt optimizations.
PowerArtist can accept power intent formats such as CPF and UPF together with the RTL design description. The user can then change the design partitioning, power supplies, or clock gating directives and quickly re-analyze the design to monitor changes in power consumption. Once the design architecture is finalized, PowerArtist-XP can write out CPF or UPF directives for the downstream flow.
Figure 7: Power prototyping enables ‘what-if’ analysis to monitor effects of SOC-level and downstream power optimization techniques
With a comprehensive set of features within the Analyze-Visualize-Reduce framework, PowerArtist-XP is the most complete RTL design-for-power solution enabling maximum power savings, in minimum time and with minimum design impact.