- Products
- PowerArtistRTL Power Reduction, Analysis, Debug, and RPM Generation
- RedHawkSoC Dynamic Power, Advanced Low Power, Reliability, and Chip-Package Co-design
- TotemAnalog/Mixed-Signal Dynamic Power, Substrate Noise, EM, and ESD
- SentinelChip-Package-System Power/Signal Integrity, IO-SSO, Thermal, and EMI
- ResourcesTechnical Papers and Presentations, Contributed Articles and Conference Papers, Webinars and Videos
- Flows
- Ultra Low PowerPower methodology for ultra-low-power designs
- IP IntegrationPower methodology for IP Integration initiative
- Chip-Package-SystemPower methodology for giga-hertz performance
- Support
- Community
- CustomersServing the industry’s leading electronics companies
- PartnersFoundry, IP, EDA, Industry Alliances
- Blog
- Chip-Package-System User GroupConvergence for Power, Noise, and Reliability
- Company
- About ApacheOverview, Milestones, Achievements
- News
- Events
- Employment
- Global Offices
PowerArtist
HIGHLIGHTS
RTL Design-for-Power for Mobile SoCs: Best Practices - Educast
SoC Power Budgeting Using RTL Power Models - Educast
Apache Customers Speak About the Benefits of PowerArtist
A user study of Apache PowerArtist RTL power reduction techniques
Two Users on Apache PowerArtist Because PrimeTime-PX is Not Enough
Why We Switched from Atrenta Spyglass Power to Apache PowerArtist
PowerArtist Resources
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Following is a list of whitepapers available for the PowerArtist platform. Access to these documents requires an Apache account. If you already have an account, please login. If you wish to request a new account, click on the Whitepaper you are interested in and you will be taken to the account registration page. Please allow 24 hours for access to Apache resources.
Whitepapers
- Electronic Power and Thermal Management
This paper presents a comprehensive set of tools and methodologies that can contribute to addressing the challenges of thermal and power management encountered in next-generation unmanned systems
- RTL Design-for-Power Methodology
This white paper presents a design-for-power methodology, beginning early in the design process at the Register Transfer Level (RTL) for maximum impact on power.
Webinar Presentations
- PowerArtist™ - RTL Power Analysis, Reduction, and Debug
This webinar describes how PowerArtist helps designers meet power budget requirements and increase the power efficiency of their ICs by enabling analysis, reduction, and optimization early in the design cycle,
- A Design-for-Power Methodology: RTL Power Analysis and Reduction
This webinar describes PowerArtist, a comprehensive design-for-power methodology beginning at RTL. This methodology includes tradeoff analysis for micro-architectural decisions, “power debug” to isolate conditions causing excessive power consumption, application of analysis-driven power reduction techniques for RTL power refinement, and rigorous power regressions at full-chip level to ensure power efficiency of the entire design.
