- PowerArtistRTL Power Reduction, Analysis, Debug, and RPM Generation
- RedHawkSoC Dynamic Power, Advanced Low Power, Reliability, and Chip-Package Co-design
- TotemAnalog/Mixed-Signal Dynamic Power, Substrate Noise, EM, and ESD
- SentinelChip-Package-System Power/Signal Integrity, IO-SSO, Thermal, and EMI
- ResourcesTechnical Papers and Presentations, Contributed Articles and Conference Papers, Webinars and Videos
Ultra Low Power
Related Articles and News
SoC Power Budgeting Using RTL Power Models - EETimes Educast
Power is at the forefront of semiconductor design today whether a device is handheld or tethered. Yet, the gap between what the power supply can deliver versus what the design consumes is widening due to an insatiable push on device integration. Using traditional gate-level methodologies will be too late for addressing this challenge. The only way to achieve the ultra-low-power goals is to address power budgeting early, during the RTL (Register Transfer Language) phase, as a key design consideration.
Power management is not limited to just lowering power. The power delivery network (PDN) is critical to the power integrity of an SOC. As the PDN becomes increasingly complex with multiple low power modes and transitions, it must withstand the worst power scenarios, while avoiding under- and over-design. Using traditional guesstimates for early analysis and gate-level simulation-based methodologies for sign-off are no longer viable. To minimize cost, ensure competitiveness and mitigate risks of voltage-induced silicon failures, PDN design needs realistic power numbers and worst case current scenarios early in the design flow.
Apache Ultra-Low-Power Methodology addresses today’s complex SOCs:
RTL Power Analysis, Debug, and Reduction with PowerArtist:
- Understand and lower power consumption early, efficiently, and effectively with a powerful graphical environment
- Reduce clock, memory and datapath power with a range of sequential and combinational automatic techniques
- Make reliable early power-related design decisions with power-smart, physical-aware PowerArtist Calibrator and Estimator (PACE™) models
- Track power via regressions throughout the design flow
RTL to Physical Power Integrity with PowerArtist RTL Power Model (RPM™)
- Perform early power grid and package prototyping before chip layout is available
- Increase power integrity sign-off coverage with worst case power cycles rapidly identified from millions of RTL vectors
- Seamless model-based flow from PowerArtist to RedHawk™ with RPM, and RedHawk to Sentinel™ with Chip Power Model (CPM™)
Figure 1: Apache Ultra Low Power flow
RTL Power Analysis, Debug, and Reduction
PowerArtist™, the industry’s leading RTL power management solution enables RTL designers to understand the where, the when, and the how of power and activity. PowerArtist provides comprehensive simulation vector analysis, RTL power analysis, and automatic RTL power reduction for a complete RTL design-for-power solution. It leverages built-in RTL power analysis for precise analysis-driven power reduction.
Figure 2: PowerArtist Use Model in the Ultra-Low-Power Design Flow
RTL power analysis relies on PowerArtist Calibrator and Estimator (PACE) technology. These statistical models deliver RTL power by accounting for design methodologies and tools in the implementation flow. They enable power-related design decisions reliably and early in the design flow. Unlike traditional methodologies that rely on guesstimates and timing analysis intended inputs, PACE models are designed specifically for power and contains physical design information for predictable RTL power accuracy.
With a comprehensive set of power reduction techniques and a range of visual debug diagnostics, PowerArtist is the low power design tool for RTL engineers. With PowerArtist, a designer can quickly identify where power is being consumed, what it takes to reduce it, and control changes through a powerful user-friendly graphical cockpit, PowerCanvas. Depending on the reduction technique, PowerArtist can automatically rewrite power-optimized RTL, output synthesis constraints, or guide the user through manual RTL edits. The automatic RTL changes preserve the original RTL formatting by making precise, surgical changes to the code.
Figure 3: PowerArtist Interactive Power Debug Environment
RTL Power Model for Physical Power Integrity
PowerArtist’s RTL Power Model, RPM™, is a first-in-class innovative technology that bridges the gap between RTL design and physical power integrity. It enables early PDN and package prototyping as well as strengthens sign-off coverage for power integrity analysis.
Figure 4: Apache's RTL to Physical Power Integrity Flow
RPM FastFrame technology rapidly identifies power-critical cycles from millions of RTL vectors. It then encapsulates power, parasitic and additional proprietary data for these cycles for power integrity analysis.
Using the RPM, RedHawk constructs a transient current waveform enabling identification of high dynamic voltage drop hotspots even before chip layout is available. RedHawk™ can also create an early Chip Power Model (CPM™) for early chip-package co-design enabling key decisions such as routing layers and decap.
Figure 5: Package resonance frequency analysis using CPM from RPM, before layout is available
Figure 6: Sensitivity analysis of package resonance frequency versus decap
The RedHawk™ power integrity analysis platform enables designers to validate and sign-off the power grid of their designs from noise and reliability considerations. The use of power reduction technologies like power and clock gating can adversely impact the power grid noise in the circuit. For example, turning on and off the clock tree network introduces significant change in the current signature of a design, which along with the package inductance, can cause high Ldi/dt induced voltage drop. By using proprietary extraction and simulation technologies, RedHawk can simulate even the largest of designs at pico-second time-domain resolution using either the test-vectors from RTL simulations through RPM or its Vectorless engine. In addition, its Explorer interface allows designers to identify the root-cause of dynamic voltage drop issues and provides an environment for exploring fixes that can be verified through incremental analyses before committing to layout.
Ultra Low Power Flow
The successful design and delivery of an ultra-low-power chip requires a comprehensive Design-for-Power methodology that spans the entire design process. Early RTL power analysis provides significant benefits that impact power consumption. In addition, RTL power analysis can be utilized to provide early data for PDN/package cost-sensitive design decisions and to identify power-critical switching scenarios. Layout-based power integrity analyses quantify the success of the RTL optimizations and ensure the containment of voltage drop in the chip. Finally, power must be tracked and monitored through the design flow to avoid power bugs from creeping in. Apache’s portfolio of products including PowerArtist, RPM, RedHawk, Chip Power Model (CPM), and Sentinel provide a seamless RTL to Physical power methodology enabling ultra-low-power design.