- PowerArtistRTL Power Reduction, Analysis, Debug, and RPM Generation
- RedHawkSoC Dynamic Power, Advanced Low Power, Reliability, and Chip-Package Co-design
- TotemAnalog/Mixed-Signal Dynamic Power, Substrate Noise, EM, and ESD
- SentinelChip-Package-System Power/Signal Integrity, IO-SSO, Thermal, and EMI
- ResourcesTechnical Papers and Presentations, Contributed Articles and Conference Papers, Webinars and Videos
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The dominant theme in today’s SoC designs is "integration of various disparate circuits in the same piece of silicon." This is done for a variety of reasons such as higher speed, tighter control, and increased product differentiation. Highly integrated circuits include multiple high-speed application processor cores, image processors, radios, memories, and I/O interfaces. These SoCs target a broad range of applications, from wireless handheld devices to desktops/servers to automotive control systems.
Achieving a successful design often comes with its own set of challenges, such as merging sensitive analog circuitry with high-speed digital logic on the same piece of silicon, or designing and manufacturing issues at the advanced process nodes. Another challenge is the ability to share information and knowledge between their disparate design flows and methodologies to ensure that the design will work to specification and at the lowest cost.
Traditionally, designers have relied on Spice-based simulations on the design (or part of it), without any consideration of how it will be used at the SoC level, or regard for the noise environment where it will be placed. Usually IP validation and sign-off are done using DC analyses, or sometimes with no analysis, just using visual plot checks as reference. Very often the analysis of the SoC digital logic does not include any analog circuit information. In addition, most of the SoC analysis performed does not include any package and/or board models. With each of the design teams (analog, SoC and package) operating independently, the design not only ends up with additional margin, but also with added cost in each area and becomes susceptible to failure due to noise coupling from one domain to another.
Power, Noise and Reliability Requirements for IP Integration
A power, noise, and reliability methodology targeting the design, validation, and cost reduction of a highly integrated mixed-signal and/or SoC design requires the following capabilities.
IP level validation
- Design connectivity analysis targeting poor routing, missed via opportunities, etc.
- Power noise sign-off (DC, transient) including top level connectivity information
- Reliability validation covering power/signal EM and ESD (DC and transient)
- Model creation for SoC level analysis
SoC level validation
- Full-chip DC and transient analysis, including IP models for voltage noise sign-off
- Package and/or PCB model inclusion
- Reliability validation including power/signal EM and ESD
- Chip Power Model (CPM™) creation for system level validation and optimization
Substrate noise coupling analysis
- Extraction and modeling of substrate parasitics
- Modeling of current injection, propagation and attenuation
- Time and frequency domain analysis for sensitivity analysis, design verification and planning
Totem™: Transistor-level Power, Noise and Reliability
Totem™ is a transistor-level power, noise and reliability analysis and IP model generation platform. Using industry standard inputs for layout and design netlist, it helps designers validate their IP or custom circuit designs for power, voltage drop, electromigration (power and signal line), ESD, and substrate noise coupling. Totem provides a highly functional and innovative user interface that allows designers to perform all these analyses by cross-probing the results onto the layout. Once the design issue is identified, Totem enables incremental what-if experiments on the layout to guide in identifying a proper fix before implementing it in the layout.
Totem provides the following capabilities and functionalities to enable the design and optimization of analog/mixed-signal designs, or the IP targeting highly integrated SoC designs.
- Integrated extraction (power grid RLC) and transient simulation engine with silicon validated results
- Simultaneous multi-domain analysis
- Layout-based debug tool with interface similar to industry standard layout editors
- Configurable shortcut buttons
- Flexibility to view the results on a net-by-net and layer-by-layer basis
- Several maps to understand and analyze the hotspots
- Innovative Short Path Tracing technology to highlight current flow path from power source to the devices
- Bottleneck report highlighting wire segment or via with the highest resistance, resulting in significant voltage drop
- Dynamic analysis capability to query voltage drop waveforms for any device over time
- Multi-frame debug window and tight cross probing between different views
- Integrated EM analysis
- Power EM targeting DC (average) and transient (RMS and peak) analyses
- Signal EM using a true transient analysis methodology
- Industry's only layout-based ESD analysis
- Connectivity analysis for HBM, MM, and CDM events
- Point-to-point resistance checking
- Current density validation
- Time domain (IP level) CDM discharge modeling
- Multi-frame debug window and tight cross probing between different views
- Substrate noise coupling
- Substrate RC network creation
- Simulation of noise injection, its propagation through the substrate and its attenuation at the guard structures
- Early planning, design exploration, and sign-off analysis support
- IP model creation
- Captures key electrical and physical parameters
- Ability to embed IP sign-off criteria
- Supports full transistor-level granularity or SoC level macro-model views
RedHawk™: Full-chip SoC-level Power, Noise and Reliability
RedHawk™ is the industry standard full-chip SoC-level power, noise and reliability analysis platform. With its integrated power calculation, extraction (power grid RLC), simulation (transient, DC, low power) and model creation (CPM™) technologies, it allows designers to validate their complex SoCs by bringing in IP models, either transistor-level detail or macro-views, to validate their connectivity to the SoC, assess the impact of their switching on the rest of the design, and quantify the impact of switching of peripheral logic on the IP through power grid and/or substrate coupling. RedHawk's Explorer offers the industry’s first fully-automated power, noise and reliability hotspot analysis.
RedHawk includes several key technologies:
- Highest capacity and speed with all domains solved simultaneously
- Silicon validated results
- Voltage drop analysis (IR, dynamic) for functional and test-mode
- Low-power simulations (rush-current, clock gating, voltage island)
- Reliability validation for power and signal EM
- Full-chip ESD integrity validation for HBM, MM, CDM
- Mixed transistor (through CMM) and cell-based design analysis
- Automatic design weakness and root-cause identification
- Chip Power Model (CPM) creation for package/system sign-off
Cross-Domain Data Exchange
One of the challenges faced by design teams is the ability to share information and knowledge between their disparate design flows and methodologies to ensure that their design will work to specification, and at the lowest cost. Apache's power, noise and reliability platforms provide a methodology for designers to validate their respective designs (block, IP, SoC) and to create models (CMM: Custom Macro Model or CPM: Chip Power Model), which can then be used for analysis and sign-off at the next higher level (SoC and Package/System level), respectively.
As designers look to achieve higher levels of integration on their SoC designs, Totem and RedHawk platforms provide them with the solutions they need to ensure that their IP and SoC designs will operate to specification, meet the reliability guidelines, and other design criteria.