- Products
- PowerArtistRTL Power Reduction, Analysis, Debug, and RPM Generation
- RedHawkSoC Dynamic Power, Advanced Low Power, Reliability, and Chip-Package Co-design
- TotemAnalog/Mixed-Signal Dynamic Power, Substrate Noise, EM, and ESD
- SentinelChip-Package-System Power/Signal Integrity, IO-SSO, Thermal, and EMI
- ResourcesTechnical Papers and Presentations, Contributed Articles and Conference Papers, Webinars and Videos
- Flows
- Ultra Low PowerPower methodology for ultra-low-power designs
- IP IntegrationPower methodology for IP Integration initiative
- Chip-Package-SystemPower methodology for giga-hertz performance
- Support
- Community
- CustomersServing the industry’s leading electronics companies
- PartnersFoundry, IP, EDA, Industry Alliances
- Blog
- Chip-Package-System User GroupConvergence for Power, Noise, and Reliability
- Company
- About ApacheOverview, Milestones, Achievements
- News
- Events
- Employment
- Global Offices
News
2011
Low Power, High Performance - ANSYS Advantage
Apache's Totem is selected by FSL for reliability analysis (Japanese) - Electronic Journal Daily News
Reliability Concerns Grow - Low-Power Engineering Community
Cell Phone Radiation: Taboo Topic, Interesting Science - Low-Power Engineering Community
Playing The Voltage Game - Low-Power Engineering Community
Experts At The Table: Managing Power At Higher Levels Of Abstraction (Part 3) - Low-Power Engineering Community
Ansys: A play on power efficiency - MSN Money
Getting a Jump on Power Integrity - FPGA Journal
Experts At The Table: Managing Power At Higher Levels Of Abstraction (Part 2) - Low-Power Engineering Community
Apache Design Announces the RTL Power Models (Japanese) - Nikkan Kogyo Business Line
Accuracy Vs. Time To Market - Chip Design
RTL Power Models - SemiWiki.com
Apache Comes Out with an RTL Power Flow - EETimes
Experts At The Table: Managing Power At Higher Levels Of Abstraction (Part 1) - Low-Power Engineering Community
Noise Coupling - SemiWiki.com
Redefining Systems Around Power - Low-Power Engineering Community
Thermal Modeling Held Back By Outdated Standards - Low-Power Engineering Community
Best in class will thrive in new spending environment - EETimes - Military/Aerospace
A New Approach to Power Noise Analysis in Analog/Mixed-Signal Designs - ChipEstimate.com
GTC 2011 - Vic Kulkarni interview with Sean O'Kane - ChipEstimate.TV
Heat Wreaks Havoc - Low-Power Engineering Community
Limits For TSVs In 3D Stacks? - Low-Power Engineering Community
2.5D and 3D designs - SemiWiki.com
EDA acquisitions point the way to long-elusive growth - DSP-FPGA.com
Top 5 Reasons for Wasting Power - SemiWiki.com
ANSYS/Apache - SemiWiki.com
Apache Update: Five Important Questions - Low-Power Engineering Community
Design For Power Methodology - Low-Power Engineering Community
EETimes DAC360 Video - Vic Kulkarni - EETimes
ANSYS Acquires Apache Design Solutions - Design News
Apache and AWR Acquisitions Offer Growth to the EDA Industry - EE Daily News
The AWR, Apache, and Verigy Acquisitions - Gabe on EDA
Show Me the Money - The Valuation of Apache Design Solutions - EE Daily News
Ansys Buys Apache - System-Level Design
Smartphones in the BRICs - SemiWiki.com
5 Ways To Cut Power - Low-Power Engineering Community
Managing Physical Effects - Low-Power Engineering Community
Experts At The Table: Power Budgeting, Part 3 - Low-Power Engineering Community
GlobalPress Summary: Analyze and Optimize the Power IC and Systems (Swedish) - Elektronik i Norden
Experts At The Table: Power Budgeting, Part 2 - Low-Power Engineering Community
Electro-static Discharge (ESD) - SemiWiki.com
The First EDA IPO in a Decade: Apache Design Solutions - Seeking Alpha
Experts At The Table: Power Budgeting, Part 1 - Low-Power Engineering Community
Extraction, Power And Final Silicon - Low-Power Engineering Community
Power Budgets: Where Is The Low-Hanging Fruit? - Low-Power Engineering Community
Silicon Valley in the sign of changing market priorities (German) - Elektronik Report
Apache at DAC - SemiWiki.com
Chip Power Models - SemiWiki.com
Semiconductor RTL Power Analysis: the Sweet Spot - SemiWiki.com
Chip-Package-System (CPS) Co-design - SemiWiki.com
Rationalization For Power - Low-Power Engineering Community
Power Issues In 3D - Low-Power Engineering Community
Wanted: ESL Power Design Flow - Low-Power Engineering Community
ESL Power Optimization Flow Requires Ecosystem - Low-Power Engineering Community
Advanced Modeling Technologies For Chip, Package, System Co-Analysis And Co-Optimization - Low-Power Engineering Community
My Spring Silicon Valley Semiconductor Report (3): 3DIC is hot (Chinese) - Nikkei BP TechOn! China
Jay Vleeschhouwer on the EDAC Market Report - Gabe on EDA
The right time for the IPO (German) - Elektroniknet.de
Andrew Yang's Presentation at Globalpress Electronic Summit - SemiWiki.com
Power Noise Analysis Solution: Co-analysis Environment Through System (Japanese) - Semiconductor Industry News
A Tale Of Two Standards - Low-Power Engineering Community
Treat ICs, Packages, And PCBs As System Designs - Electronic Design
The Shocking Side Of 3D - Low-Power Engineering Community
Apache Introduces Latest PDN Model (Japanese) - EETimes Japan
No More Netlist Hacking - Low-Power Engineering Community
The Missing Pieces In Power Modeling—And Who’s Going To Provide Them - Low-Power Engineering Community
Apache Announces the Release of CPM v2.0, Its Next Generation Chip Power Model (Japanese) - Nikkan Kogyo Business Line
Apache Releases CPM v2.0 at DesignCon - EE Times
Chip Package System (CPS) - SemiWiki.com
Packaging’s Power Play - Low-Power Engineering Community
Power Model Complexity Grows - Low-Power Engineering Community