- Products
- PowerArtistRTL Power Reduction, Analysis, Debug, and RPM Generation
- RedHawkSoC Dynamic Power, Advanced Low Power, Reliability, and Chip-Package Co-design
- TotemAnalog/Mixed-Signal Dynamic Power, Substrate Noise, EM, and ESD
- SentinelChip-Package-System Power/Signal Integrity, IO-SSO, Thermal, and EMI
- ResourcesTechnical Papers and Presentations, Contributed Articles and Conference Papers, Webinars and Videos
- Flows
- Ultra Low PowerPower methodology for ultra-low-power designs
- IP IntegrationPower methodology for IP Integration initiative
- Chip-Package-SystemPower methodology for giga-hertz performance
- Support
- Community
- CustomersServing the industry’s leading electronics companies
- PartnersFoundry, IP, EDA, Industry Alliances
- Blog
- Chip-Package-System User GroupConvergence for Power, Noise, and Reliability
- Company
- About ApacheOverview, Milestones, Achievements
- News
- Events
- Employment
- Global Offices
News
News
Press Releases
Coverage
RTL Power Estimation at DAC - SemiWiki.com
How much of the chip does IP fill? - EETimes
Executive Briefing: Andrew Yang - Low-Power High-Performance Engineering Community