DAC Speakers, Panels, and User Tracks

Join Apache experts and customers at the following conference activities.

Tuesday, June 15

User Track Posters: 2nd Floor Foyer, Adjacent to 208AB
1:30 PM – 3:00 PM

• Analysis of Power Delivery Network of Multiple Stacked ASICs using TSV and Micro-Bumps
• ESD Verification and ESD Aware Design Optimization for Complex System-on-Chip Design

Exhibitor Forum: Booth #1562
3:15 PM – 3:50 PM

Chip-Package-System (CPS) Co-design/Co-analysis using Chip Power Model (CPM)
Bhavana Thudi, Apache Design Solutions

Exhibitor Forum: Booth #1562
3:55 PM – 4:30 PM

Reliability Verification for the Post 45nm Era
Arvind Shanmugavel, Apache Design Solutions

Wednesday, June 16

Technical Panel: Room 207AB
9:00 AM – 11:00 AM

3D Stacked Die: Now or Future?
Moderator:
    Andrew Yang, Apache Design Solutions
Panelists:
    Pol Marchal, IMEC
    Riko Radojcic, Qualcomm
    Myung-Soo Jang, Samsung
    Philippe Magarshack, STMicroelectronics
    LC Lu, TSMC

Exhibitor Forum: Booth #1562
1:00 PM – 1:35 PM

RTL Design for Power using PowerArtist-XP
William Ruby, Apache Design Solutions

Thursday, June 17

User Track: Room 208AB
9:00 AM – 11:00 AM

• Package/PCB Aware On-Die Power Grid Noise Analysis
• Power Delivery Network Design and Analysis
• Power Noise Mitigation Strategy from RTL Perspective on MTCMOS Design
• An Accurate and Efficient SSO/SSN Simulation Methodology for 45nm LPDDR I/O Interface