Apache's Chip-Package-System (CPS) Workshops

Date: Wednesday, February 1, 2012 - 10:15am - 4:00pm PST
Location: DesignCon in Santa Clara, CA

Chip-Package-System (CPS) Workshops Sponsored By Apache Design

The CPS Workshops, sponsored by Apache Design, are open forums for designers to exchange the latest ideas and information on current technologies for chip and package modeling, and system level verification for SI, PI, EMI and thermal. Two in-depth workshops will bring together key semiconductor companies and system houses from the electronics industry to share their expert perspectives and best practices on “CPS Methodology for Cost-Down and/or Reliability” and “CPS for 3D-IC and Power-Thermal-Mechanical-Electrical Applications”. 

There is no cost to attend the workshops, but registration is required. Register for your complimentary Expo Pass and select one or both workshops during the registraiton process.

CPS Methodology for Cost-Down and/or Reliability
Date & Time: Wednesday, February 1, 2012 – 10:15am-12:15pm
Location: Ballroom H, Santa Clara Convention Center
Featuring Presentations By: Qualcomm, Cisco and Intel

Meeting the performance and cost demands of today’s chip designs requires a comprehensive chip-package-system approach to analysis. A complete methodology should include accurately characterized models of all system aspects including chip, package and board, while providing simulation capabilities to enable engineers with enough knowledge and confidence to make optimal cost reduction, performance, and reliability decisions for their designs.

In this informative and educational workshop, representatives from the industry’s top semiconductor and system design companies will share their insights and expertise in the area of chip-package-system (CPS) convergence, and will discuss various aspects of analysis methodologies and technologies in terms of modeling, extraction and simulation. Topics will include comprehensive global power delivery optimization at the chip, package and board levels, system-level signal integrity analysis, along with case studies and real design examples.

Featured Speakers:

Dr. Mondira Pant, Intel
Power Delivery Network Design of Modern Microprocessors: Getting it Right the First Time

Dr. Amit Agrawal, Cisco
Signal and Power Integrity Challenges for High Speed System Board Design

Thao Pham, Intel
Power Grid Parasitic Impact on System Level Power Integrity

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CPS for 3D-IC and Power-Thermal-Mechanical-Electrical Applications
Date & Time: Wednesday, February 1, 2012 – 2:00pm-4:00pm
Location: Ballroom H, Santa Clara Convention Center
Featuring Presentations By: Micron, LSI and Xilinx

3D stacked die and 2.5D Silicon Interposer chip designs with through-silicon vias (TSVs) have emerged as upcoming technologies, enabling designers to meet the performance, power, and form factor demands of today’s ICs. While it reduces the overall footprint of design real estate, 3D architecture also significantly improves vertical routing density and reduces wire length, thus allowing for improvements in communication time, robustness against signal integrity issues, and power consumption. However, 3D-IC designers face unique challenges such as thermal-induced EM and reliability issues, along with place and route congestion due to TSV insertion. To combat these challenges and achieve design closure requires 3D-ready modeling and simulation techniques.

This interactive workshop features experts from the industry’s leading semiconductor and system design companies who will examine the various modeling and simulation challenges in 3D-IC design. Methodologies for the analysis of power delivery network, chip-to-chip communication, and thermal integrity will be covered using real case studies on designs.

Featured Speakers:

Dr. Tim Hollis, Micron
Modeling and Simulation Challenges in 3-D Memories

Ivor Barber, LSI
Modeling and Simulation Challenges in Evolving 3D-IC Formats

Dr. Simon Burke, Xilinx
Challenges and Solutions to Practical 3D-IC Design

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