- PowerArtistRTL Power Reduction, Analysis, Debug, and RPM Generation
- RedHawkSoC Dynamic Power, Advanced Low Power, Reliability, and Chip-Package Co-design
- TotemAnalog/Mixed-Signal Dynamic Power, Substrate Noise, EM, and ESD
- SentinelChip-Package-System Power/Signal Integrity, IO-SSO, Thermal, and EMI
- ResourcesTechnical Papers and Presentations, Contributed Articles and Conference Papers, Webinars and Videos
Date: Wednesday, September 26, 2012 - 11:00am - 12:00pm PDT
This webinar will focus on co-simulation methodologies for time and frequency domain simulations. A theoretical review of package/PCB modeling will be presented with a revisit of ABCD networks as related to S and Z parameters. An overview of chip-level extraction will be given with a discussion on how to include chip models in a system-level simulation. The goal is to provide engineers with methods that successfully design power delivery networks with the chip to ensure system metrics are met in context of the system as a whole, rather than individual parts.
What attendees will learn:
- Power Delivery Network (PDN) design requirements
- ABCD Matrix theory
- SYZ Matrix theory
- Chip-level Extraction
- Effect of Chip inclusion on time and frequency domain system simulation
For more information and to register, click here.