Apache Technology Forum 2010

Date: Friday, October 15, 2010 - 3:00pm CST - Thursday, October 21, 2010 - 3:00pm CST
Location: Taiwan, Japan, Korea

Power Methodology from RTL Design to Chip-Package Sign-off 

Overview

In this full-day multi-track technology seminar, Apache Design Solutions, along with industry leaders, will share proven methodologies for addressing the most critical design challenges faced by engineers today – power and noise management for electronic designs. Presentations include technology roadmap for 28nm processes and beyond, advanced reliability solutions for electrostatic discharge (ESD) and dynamic electro-migration (EM), and 3D-IC design impact on power, signal, and thermal integrity. Afternoon tracks provide in-depth technical discussions on two key requirements for design methodology – achieving ultra-low power design targets while maintaining design integrity, and meeting system cost and performance needs through integrated chip-package-system design flow. Both presentations will walk the audience through a complete flow using real design examples to provide practical use information that can be applied to their current design projects.

Taiwan

• Date: October 15, 2010
• Venue: Ambassador Hotel - Hsinchu, Taiwan
• For more information and to register

Japan

• Date: October 19, 2010
• Venue: Shin Yokohama Prince Hotel - Yokohama, Kanagawa, Japan
• For more information and to register

Korea

• Date: October 21, 2010
• Venue: Grand Intercontinental Hotel - Seoul, Korea
• To register