DAC Presentations and Demonstrations

Presentation Schedule:

• Monday, June 14
• Tuesday, June 15
• Wednesday, June 16

Monday, June 14

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Tuesday, June 15

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Wednesday, June 16

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Customer Presentations

RTL Power Analysis and Reduction

A Design for Power Methodology: The LSI Experience
Ruggero Castagnetti, LSI

This presentation will review the Design for Power methodology adopted by LSI with emphasis on RTL level power estimation and reduction techniques. Also presented will be results from past work, along with a roadmap on continued areas of collaboration between LSI and Apache.    <Register>

Power Integrity and Signoff for SoC, Analog/Mixed-Signal, and 3DIC Designs

A Foundry’s View of Power Integrity Closure for 3DIC, 28nm, and More
Willy Chen, Program Manager, EDA Partnership and Collaboration Program, Design and Technology Platform, TSMC

In this presentation, TSMC will provide an in-depth view of the long term collaboration with Apache in addressing power integrity, an issue that continues to evolve from chip, to package, to SiP/3DIC. TSMC will share solutions that designers can benefit from in various programs including Reference Flow, Integrated Sign-off Flow, Interoperable technology files such as iRCX, and EDA qualifications.    <Register>

Use of Advanced VectorLess Options for Power Integrity Validation in TI High Performance Designs
Asif Mahbub, ASIC Physical Design, Texas Instruments

Lack of data from logic simulation (VCD) to perform dynamic power noise analysis is a known and vexing problem. This presentation will discuss advanced techniques used by TI in their high performance designs for creating sets of realistic switching scenarios for performing IP and full-chip level dynamic power integrity analysis, allowing for chip layout and package issue identification and fixes early in the design process.    <Register>

Power and Thermal Variation Aware Design Methodology and Challenges
Fumihiro Minami, STARC

This presentation will cover advanced timing analysis that considers the impact of dynamic voltage drop and the thermal variation. Dynamic voltage drop will consider the simultaneous switching noise of memory blocks whose models were generated by Totem. Thermal impact is based on chip’s temperature distribution analysis performed by Sentinel-TI. The presentation will also include experimental results with good accuracy and turnaround time.    <Register>

Reliability Solutions for EM and ESD

Reliability Validation Challenges and Solutions for Nanometer Designs
Remy Chevallier, Expert in Reliability and Tools for Libraries, Team Leader, STMicroelectronics

In this presentation, ST will outline some of the challenges they see impacting device and wire reliability in 45nm processes. Specifically there will be a focus on analysis methodologies and solutions targeting electromigration and other issues affecting the design in these technology nodes.    <Register>

Analysis and Mitigation of ESD Induced Failures for Advanced IP Designs
Richard Rouse, Distinguished Engineer, MoSys, Inc.

The impact of ESD induced failures, especially for I/O circuits is increasingly felt for advanced process nodes. This presentation will outline the approaches MoSys is taking in modeling and predicting current discharge paths and in identifying and fixing layout issues that can impact their circuit from an ESD event. The presentation will illustrate MoSys' methodology through examples and silicon results.    <Register>

Chip-Package-System Co-design / Co-analysis

DDR-based I/O Interface Design and Verification Techniques
Dr. Souvik Mukherjee, CAD/Methodology Engineer, Texas Instruments

This presentation will outline the techniques and methodologies used by TI for modeling and simulating the LP DDR interface used in the TI OMAP products to ensure accurate prediction of system jitter by incoporating both power and signal integrity issues. The presentation will also include data from using the proposed flow on past and ongoing projects, along with silicon correlation results.    <Register>

Package and PCB Model Extraction Using a 3D Full-wave Technology with Correlation to Measurement

In this presentation, the use of a package and PCB level 3D Full-wave extraction and modeling technology will be outlined both for extraction and for chip-package-system co-simulation needs. Usage, performance, and flow descriptions will be shared. Correlation of simulation result to measurement for multiple configurations of the package and board will be shared.    <Register>

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Product Presentations and Demonstrations

PowerArtist

A comprehensive RTL design for power platform with fully-integrated advanced analysis and automatic reduction. The presentation will focus on PowerArtist-XP and its unique Analyze-Visualize-Reduce framework delivering maximum power savings for complex SoCs and IPs. <more>
<Register: June 14>   <Register: June 15>   <Register: June 16>

RedHawk

A full-chip dynamic power integrity solution from early design prototyping to sign-off. The presentation will cover RedHawk product family including SoC power, advanced low power, and chip power model generation. It will also touch on reliability solutions including electro-migration (EM) and electro-magnetic interference (EMI). <more>
<Register: June 14>   <Register: June 15>   <Register: June 16>

Totem

A transistor-level power/ground noise analysis and verification solution for static and dynamic power integrity from early stage design to sign-off. The presentation will discuss products and technologies for analog and mixed-signal IP verification, model creation, and power analysis with consideration for impact of substrate noise. <more>
<Register: June 14>   <Register: June 15>   <Register: June 16>

PathFinder

A newly introduced electro-static discharge (ESD) integrity solution targeted at addressing reliability challenges faced by nanometer designs. The presentation will include the industry’s first layout-based ESD solution for full-chip sign-off and circuit level optimization. <more>
<Register: June 14>   <Register: June 15>   <Register: June 16>

Sentinel-NPE, Sentinel-PSI

A 3D package and PCB power and signal integrity solution. The presentation will highlight Apache’s high performance, high capacity quasi-static and full-wave electromagnetic modeling and analysis products, with the ability to perform DC, AC, and transient simulations in a single environment. <more>
<Register: June 14>   <Register: June 15>   <Register: June 16>

Sentinel-SSO, CPM

A high-speed I/O noise analysis and chip-package-system co-design solution. The presentation will cover I/O-SSO methodology and solutions that incorporates Apache’s high-capacity I/O sub-system timing and noise analysis solution and SPICE accurate chip power model generation tool. <more>
<Register: June 14>   <Register: June 15>   <Register: June 16>

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Practical Application Tutorials

Design RTL for Low Power

This tutorial will guide you through RTL power analysis and reduction flow utilizing PowerArtist. It will demonstrate how you can identify and fix Power Bugs in your design with a comprehensive analyze-visualize-reduce environment.   <Register>

Power Grid Prototyping and Design Exploration

This tutorial will demonstrate how to perform power design exploration - trading off power, performance, and area – to determine the optimal power grid design early in the process.   <Register>

Power Grid Integrity Analysis and Debug with RedHawk Explorer

This tutorial will walk you through power integrity analysis, root cause identification, and fixing and optimization of your power grid design utilizing RedHawk Explorer design debug environment.   <Register>

Reliability Analysis and Debug for EM and ESD

This tutorial will focus on analysis and debugging methodology for power and signal EM verification, and full-chip ESD sign-off and dynamic circuit optimization.   <Register>

3DIC/TSV Power and Noise

This tutorial will discuss the multi-die analysis flow utilizing RedHawk, Totem, CPM, and Sentinel product families.   <Register>

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