Home › Products & Solutions › System Power Noise Reliability › Sentinel-SSO

Sentinel-SSO

Sentinel-SSO is a high-capacity I/O sub-system timing analysis solution. It’s global I/O-SSO simulation supports entire bank of I/Os under simultaneous switching condition with SPICE-level accuracy. Sentinel-SSO accurately models all sources of noise that impact the timing of the I/O sub-system including I/O cells, decap cells, power/ground distribution network, and package and PCB parasitics.

Sentinel-SSO provides an automated flow for I/O subsystem signal and power integrity with P/G extraction of I/O power grid, handling of comprehensive package and PCB models including lumped or distributed RLCK model, as well as broadband S-parameter model, and performs automatic identification of cross-talk aggressors.

Existing I/O-SSO simulation techniques include IBIS behavioral modeling and transistor-level spice. While enabling large capacity simulation, IBIS models are known for its deficiencies in capturing power integrity impact on timing. On the other hand, transistor-level simulation cannot handle the capacity required for analyzing the global SSO effects.

Sentinel-SSO provides the capacity required to simulate an entire bank of I/O (>100) with spice-level accuracy. With Sentinel-SSO, designers can better assess the SSO impact on timing, optimize their I/O pad selections and placements resulting in efficient power/ground to signal pad ratio, and resolve system timing closure issues in high-speed parallel interfaces.