RedHawk-PSI

RedHawk-PSI is a full-chip clock network integrity (jitter) and critical path timing signoff solution for high-performance nanometer designs. It considers the concurrent and interdependent effects of power and signal integrity on clock jitter and critical path timing. Certified by TSMC's Reference Flow, RedHawk-PSI delivers cell-based ease-of-use and performance with true Spice accuracy. With RedHawk-PSI, designers gain visibility to true silicon behavior, allowing them to focus on the real timing issues.

Benefits

Quantitatively measure clock jitter noise with silicon correlated accuracy
Increase confidence in timing sign-off with accurate analysis of noise impact on clock jitter and skew
Consideration of concurrent PI and SI effects on jitter and critical path timing for realistic view of silicon behavior
True-Spice accuracy for golden timing signoff
Delivering SPICE-level accuracy within a cell-based flow

Dynamic vs. Static

Existing timing solutions are based on static methods. However, with increasing switching frequencies and lower operating voltages as designs move towards 65nm/45nm process nodes, it is no longer acceptable to ignore or approximate the “true” dynamic effects of the circuit with a static-based solution.

RedHawk-PSI is a dynamic solution with critical path analysis that is based on real waveform simulation versus a linear approximation. It uses real Vdd/Vss instance waveforms rather than effective Vdd/Vss approximation of instance supply voltages.

Real waveform simulation vs. linear approximation

Real Vdd/Vss instance waveform vs. effective Vdd/Vss approximation

Concurrent PI and SI

At 130nm and above, noise caused by signal crosstalk had the most impact on the chip’s performance, whereas at 90nm and below, noise caused by dynamic voltage drop became the main contributor. Now, at 65nm and beyond, both crosstalk and power supply noises are impacting the chip’s performance. And since from a device perspective, it cannot distinguish whether the noise is caused by crosstalk or dynamic voltage drop, the solution must be able to understand both signal and power supply noise concurrently.

SoC noise can cause real timing failures

RedHawk-PSI reads in the design database and the parasitic information, along with the static timing report, to build a Spice netlist of the clock tree network and critical path that includes all the parasitics for the nets in the path, all the coupling capacitors, and the coupled aggressor gates. To determine the real fan-out load of the aggressor drivers, RedHawk-PSI uses a non-linear MOS transistor model instead of a simplified equivalent capacitance load model. This provides much higher accuracy for crosstalk noise analysis compared to other methods.

Real fanout transistor load vs. equivalent capacitance load approximation

RedHawk-PSI accurately represent the effects of dynamic voltage drop and ground bounce on timing by performing true dynamic transient analysis of the full-chip power grid and generating sign-off quality dynamic voltage drop waveforms for each instance in the design. RedHawk-PSI utilizes the instance-specific Vdd/Vss waveforms, which is not simply a function of that cell’s switching activity, but is also dependent on neighboring cells' activity, and combines its effect with the coupling noise to accurately analyze clock jitter and critical path timing.

Cell-based Flow with True-Spice Accuracy

SPICE is the ultimate authority in silicon-correlated accurate simulation. However, with the capacity and performance limitations of traditional SPICE simulators, it is impossible to simulate an entire SoC design. In addition, it is very time-consuming and error-prone for a designer to generate a SPICE netlist that contains the clock tree network or critical path that includes the coupling network, coupling drivers and receivers, and power / ground supply. Even with a SPICE netlist, traditional SPICE simulators are limited in their capacity and performance to simulate the network.

RedHawk-PSI delivers standard-cell capacity with a SPICE-accurate simulation of clock tree networks and critical paths, including all the nanometer and high-speed effects, such as crosstalk and dynamic voltage drop. RedHawk-PSI utilizes a true-Spice simulator with proprietary BLSN (big linear, small non-linear) technology to accelerate the solving of networks that have an enormous number of linear elements, and a smaller number of non-linear elements.

RedHawk-PSI automatically generates SPICE netlist containing all the devices in the clock tree or critical path, including the parasitics in the routing and potential aggressors coupled to the nodes in the path. Then it applies instance-specific Vdd/Vss waveforms to all power and ground pins of the gates in the path, and automatically runs distributed SPICE simulation using LSF and/or Sun Grid multiple machine processing for higher throughput. RedHawk-PSI reads in, as well as outputs, standard STA formatted files for clock tree and critical path analysis.

Ultimate Timing Sign-off Solution

For designs at 90nm and below, the concurrent effects of power and signal integrity must be considered for timing signoff verification. And this must be done using a dynamic analysis methodology with true-SPICE accuracy within a cell-based flow. With RedHawk-PSI, designers are able to quickly and accurately analyze clock jitter and critical path timing for the ultimate timing signoff of their nanometer design.

Downloads Contact Us Site Map

Highlight