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RedHawk-NX

RedHawk-NX is the next generation full-chip power integrity solution re-architected to meet the capacity and performance requirements of the most advanced designs. RedHawk-NX can be used for early-stage design analysis, pre-tapeout power sign-off, and post silicon debug. It has been silicon-proven with thousands of successful tape-outs by leading semiconductor and fabless semiconductor companies.

RedHawk, with integrated transistor-level characterization, accurately analyzes the effects of simultaneous switching noise (core, memory, macro, I/O), capacitance (intentional, intrinsic, load, well), on-chip inductance, and package and system parasitics on high performance SoCs.

RedHawk enables designers to perform early-stage grid prototyping and optimization, analyze the impact of dynamic voltage drop on timing, explore and identify physical design weaknesses, and debug and repair the source of supply noise. By using RedHawk, engineers can mitigate design risks, reduce overall cost, and improve time-to-market.

Capability Highlights

• Single kernel for static IR-drop, EM, and dynamic voltage drop (DvD) for ease-of-use and quick time-to-results
• Industry’s first hierarchical dynamic technology for advanced SoC design methodology
• Multi-core architecture support leveraging the capacity and performance advantages of multiple-CPU computing systems
• Integrated full-chip parasitics extraction including self and mutual inductance and 45 degree modeling
• Dynamic library characterization of cell, memory/macro, and I/O for Spice-level accuracy
• Package parasitics impact through integrated RLCK and S-parameter model support
• VCD and Vectorless Dynamic analysis with power, network, and timing awareness
• Full-chip true-transient dynamic simulation engine for sign-off quality-of-results
• Layout-based GUI and TCL interface
• Physical design weaknesses exploration and identification
• "What-If" analysis and optimization with built-in GUI and text interface for real-time layout changes
• Wire fixing and optimization, including non-uniform grids (Optional)
• Decoupling capacitance advisory and optimization (Optional)
• Analysis of dynamic voltage drop impact on timing and jitter (Optional)
• Chip Power Model creation for chip-package-system convergence (Optional)
• Certified in TSMC and Common Platform Reference Flows for power closure

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Dynamic Power Noise Challenges

Low power, low voltage, higher integration density and higher operating frequencies make the ICs of today and in the near future susceptible to dynamic noise induced failures. Failures such as hold-time failures during scan-mode testing due to simultaneous switching of several gates, degradation of clock network performance caused by high jitter noise, system instability from close harmonics of on-die clock frequencies and resonance frequency, etc. are all caused by simultaneous switching noise propagating through the power delivery network and its associated components.

Power supply noise consists of resistive network drop (IR drop) and inductive element induced noise (di/dt), and therefore requires a highly accurate full-chip transient simulation solution that provides a complete picture of the dynamic voltage profiles in the design. As DvD noise is affected not only by the on-die design and material properties but also by the package and board elements, especially for ICs in the 65nm and 45nm nodes, a co-design environment where package and chip designs work in tandem is critical, especially for designs employing packages with multiple dies stacked on top or side-by-side to each other.

RedHawk's silicon-proven full-chip dynamic power analysis solution considers resistive, inductive, and capacitive elements from on-die and the IC package grids, the dynamic current drawn by simultaneously switching outputs, and the capacitive loads present in the design.

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Advanced Design Methodology

RedHawk-NX delivers the industry’s first hierarchical dynamic (HD) technology allowing designers to adopt an IP-centric design methodology with various levels of abstraction while maintaining the sign-off accuracy of a flattened analysis.

RedHawk’s hierarchical approach allows for creation of models from macros, memories, or sub-blocks that can then be used for full-chip level simulations. This approach enables a productive and convenient methodology for multi-site design teams by allowing each team to analyze their design sub-blocks and pre-process the analyzed block to create model for use in full-chip simulations. The model creation Apache’s dynamic power views can be performed at various levels of abstraction to allow IP suppliers to control the protection levels of their encrypted IPs.

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High Capacity and Performance

RedHawk supports numerous techniques to deliver the highest capacity and performance full-chip dynamic power analysis. RedHawk-NX’s HD technology reduces runtime, peak memory usage, and disk space consumption by 30-50% compared to a full flat analysis, while maintaining accuracy of results to less than 2-3%. The improvements using HD is greater when sub-blocks or macros/memory modules are instantiated multiple times in the design.

RedHawk-NX also supports industry’s first hierarchical extraction technology called Mesh Pattern Recognition (MPR), which utilizes the regularity and patterns in the power grid network for data re-use and effective reduction of physical memory needs. The benefits are significant for stages of analysis that are most impacted by the size of designs such as extraction and matrix solve with database memory footprint reduction in the order of 2-3X.

RedHawk employs a database technique that allows designers to trade off run-time performance with the physical memory size of their machine. Based on the available memory space, RedHawk automatically loads the database from cache, as needed, for high-capacity high-performance analysis and verification.

Additionally by using the multiple cores that are present in today’s computing systems, RedHawk can parallelize it computation tasks and reduce the run-times by as much as 2-3X, especially for MTCMOS rush current analysis, compared to running on a single thread.

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Sign-off Accuracy

RedHawk’s integrated high-performance full-chip RLC extraction engine creates on-die power and ground grid network by working on multiple power and ground domains simultaneously. Every cell in the design is pre-characterized using SPICE simulation to model switching current waveforms and RC parasitics information for different input slew, output load, supply voltage, and operating states for the Apache Power Library (APL).

All the necessary capacitive elements in the design including cell intrinsic capacitance, load capacitance, intentional decoupling capacitance, and well capacitance are included in the simulation along with their respective resistive components. A package and board model in either the S-parameter or the RLCK format is also considered during true-transient simulation. All power and ground domains are simulated simultaneously and the switching current drawn by each cell is updated at every time step based on the effective VDD-VSS voltage seen by the cell.

RedHawk’s detailed linear representation of the non-linear elements makes SPICE accurate results possible in a full-chip level transient simulation. Typically, RedHawk’s transient simulation voltage waveforms results are within 2% of SPICE and measured silicon.

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VCD and Vectorless Dynamic

Generation of vectors that have the switching activity information for all gates in the design for use in full-chip simulation is usually not possible, especially prior to tape-out. And even if such a vector was available, simulating all the 1000’s of cycles contained in that vector would be extremely time consuming.

RedHawk transient simulation supports both gate (toggle information for every gate) and RTL (toggle information for every state and primary I/O point) vectors in the industry standard formats. When using RTL VCD, RedHawk uses its “state propagation” engine to derive the toggle activity at the other logic points. It also provides a “cycle selection” technology that scans through a VCD and identifies the relevant clock periods of interest based on several criteria like power consumption, power variation, potential impact on DvD, frequency content, etc.

To address the challenges of generating a vector early in the design phase RedHawk provides Vectorless Dynamic engine for full-chip dynamic analysis. RedHawk’s Vectorless engine generates a cycle by cycle switching scenario honoring user specified constraints such as power consumption, logic properties of the design and the cells, etc. The Vectorless engine enables designers to accurately analyze the impact of package parasitics, on-chip inductance, and decoupling capacitance on transient “hot spots”, without requiring VCD files or stimulus from the designer.

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Connectivity Verification and Weakness Exploration

RedHawk provides the capability to verify power grid connectivity issues, like shorts, opens, missing vias and other weaknesses. These connectivity issues can be debugged through the GUI and through textual reports. RedHawk network topology analysis provides insights into routing issues that can cause voltage drop hot-spots or current congestions in the design. The current flow information from the voltage supply pads to every cell or transistor is provided as an overlay on the design layout allowing one to identify cases where the “shortest” path is not being taken. All the design connectivity checks can be performed on designs that have LVS and DRC issues since RedHawk can identify the short location(s) and disconnect them from the network it constructs. This allows designers to utilize these capabilities from very early in the design flow when the data may not be completely “clean”.

As part of the static analysis capability, RedHawk will report the power for every cell, the voltage drop in every wire, via and cell, and EM/current for every wire and via in the design. It will also report the current through every power pad. If there are power gates in the design, it will report the current through and voltage at the switch terminals. From the dynamic analysis, RedHawk will report the dynamic switching current through all the pads, dynamic voltage drop for every cell, and peak and RMS current for every wire/via in the design. If there are power gates, it will report the current and voltage at the switches.

In addition to providing the results from the simulations (IR, EM, DvD), RedHawk also provides several debug and analysis features that help designers find out the cause of the issues being reported. For example, using a series of TCL commands, one can zoom to any hot-spot, obtain the amount of peak switching charge, the switching that causes it and the effective decoupling capacitance for any hot-spot. RedHawk will provide all of this information based on several categories like switching charge which can be broken down based on the type of cells, area of the design, associated domain, etc. Thus, with a combination of different reports, displays, debug and analysis options, RedHawk allows designers to isolate design weaknesses and identify their causes.

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Design Repair with “What-if” and FAO

RedHawk supports extensive "what-if" exploration within the GUI cockpit to enable power-grid exploration and to assess design tradeoffs. The easy to use, layout driven, incremental "what-if" analysis capability enables a designer to explore design fix scenarios leveraging technologies like incremental extraction providing rapid turn-around time. SoC designers can run "what-if" analysis to assess design tradeoffs, such as package RLC effects, as well as accurately determine the amount of decoupling capacitance to use and precisely where to insert the intentional capacitance. In addition, designers can explore different ways to reduce IR drop and EM violations by adding, deleting or editing power/ground pads, power straps and vias or via arrays.

Once the full-chip transient “hot spots” are exposed, RedHawk with optional FAO feature optimizes decoupling capacitance by analyzing the full-chip intrinsic parasitics and computing the additional intentional decoupling capacitance required to reduce the peak IR drop. This enables designers to determine the amount of decoupling capacitance to use and precisely how to insert the intentional capacitance near victimized "hot spots". De-cap optimization can be accomplished early in the design stage to ensure that the location and correct amount of de-cap is allocated during the placement stage. RedHawk also provides information about those decap cells that are not effective in suppressing the power noise generated on the die so designers can eliminate them from the design reducing the impact on leakage and yield.

Additionally RedHawk with FAO can be used to re-design the power grid mesh either in a local area (fixing) or over the whole chip (optimization) by specifying certain constraints. Without compromising the total voltage drop, RedHawk increases metal resources in the areas of dynamic "hot spots", while reducing the metal widths of the areas with low voltage drop to avoid over-designing. RedHawk's non-uniform grid optimization allows designers to specify constraints such as area, metal layers, and target drop to be considered for optimization. Since the optimization engine is tightly integrated with RedHawk's proven dynamic analysis engine, the designers can feel confident with the accuracy of the optimized grid.

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Design Prototyping

RedHawk allows power grid prototyping based on design specifications and technology information, to determine the on-die power grid design style and metal resource usage necessary to meet the design’s power delivery constraints. Users can build the early design database in the RedHawk environment using an extensive set of layout drawing commands, or read in the partial design information. Initial floor-plan data like placement information for the blocks or definition of regions containing certain functional units along with power consumption data for various blocks, macros, and regions can be used to perform early power analysis for the design.

RedHawk provides pad/bump placement guidance and identifies current congestion areas on the die. It also provides guidance for power-gate design and placement. Such an early prototype analysis can also lead to the creation of early models of the die called Chip Power Model (CPM). For the package and board designers, CPM model has several benefits, like visibility into the number of layers needed in the package, the pin count to design for, and the routing and via placement challenges. Even with minimal data available in the early design stages, RedHawk provides intuitive and interactive capabilities, such as mesh creation, automatic via placement, pad, switch, and de-cap placement to model different aspects of the early design.

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Unified Analysis and Debugging Environment

RedHawk provides a single unified environment for analysis and debugging of power, noise, and timing. Its layout based GUI provides designers with the flexibility and robustness required for easy-to-use yet comprehensive debugging capabilities.

From within the RedHawk environment, designers can access various views of their design, including layout view of the power density, instance power, and dynamic voltage drop. RedHawk also provides a number of waveform views such as total current and charge profile and instance-based Vdd drop and Vss ground bounce. Its full-chip movie mode playback with instance-based voltages over time assists designers in gaining access to critical information required to analyze and debug their designs.

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