RedHawk-EV with FAO

RedHawk-EV is a full-chip dynamic power analysis and optimization solution for early-stage design analysis, power signoff, and post silicon debug. It has been silicon-proven with thousands of successful tape-outs by leading semiconductor and fabless semiconductor companies.

RedHawk, with integrated transistor-level characterization, accurately analyzes the effects of simultaneous switching noise (core, memory, I/O), decoupling capacitance (intentional and intrinsic), and on-chip and off-chip (package) inductance on high performance SoCs.

RedHawk enables designers to analyze the impact of dynamic voltage drop on timing, explore and identify physical design weaknesses, and automatically repair the source of supply noise. By using RedHawk, engineers can reduce the likelihood of a design re-spin, while improving yield.

Benefits

Certified in TSMC and Common Platform Reference Flows for power closure
Highest capacity analysis with full-chip noise modeling for billions of transistors
Integrated parasitics extraction of millions of RLC components
Transient waveform analysis in hours rather than weeks of turnaround time
Proven accuracy through correlation with SPICE and measured silicon
Full-chip coverage with Vectorless Dynamic analysis
Identification of dynamic "hot spots" and their impact on timing
Accurate location of physical design weaknesses
Automatic repair of sources of noise with FAO
Robust and reliable decoupling capacitance protection
Unified analysis and debugging environment for high productivity
Reduction of wasted resources from over-designed grids
Increased yield and lower risk of silicon failure

Capability Highlights

Static IR-drop, EM, and dynamic voltage drop (DvD)
Integrated transistor-level cell, memory, and I/O characterization
Full-chip RLC network extraction, including self and mutual inductance
Vectorless Dynamic analysis with power, network, and timing awareness
Physical design weaknesses exploration and identification
Wire fixing and optimization, including non-uniform grids
Decoupling capacitance advisory and optimization
Analysis of dynamic voltage drop impact on timing
Clock-tree analysis
"What-If" analysis and optimization
Native support for GDSII memories and 45-degree geometries

Power Closure Sign-off Requirements

As designs move towards 65 and 45nm process nodes, power supply noise and its related issues become critical concern. More and more designs are experiencing timing slow-down and functional failures due to power grid noise. To address these issues, leading foundry sign-off flows have added power closure requirements.

Power supply noise consists of resistive network drop (IR drop) and inductive element induced noise (di/dt), and therefore requires a highly accurate full-chip transient simulation solution that provides a complete picture of the dynamic voltage profiles in the design. RedHawk's silicon-proven full-chip Vectorless Dynamic simulation approach considers resistive, inductive, and capacitive elements from the chip package and on-die grid, the dynamic current drawn by simultaneously switching outputs, and the capacitive loads present in the design.

Transistor-level Accuracy with Cell-based Capacity & Perfomance

RedHawk performs true full-chip transient simulation, considering all power-ground RLC parasitics, as well as the SPICE current waveforms for each cell from the Apache Power Library (APL), yielding accurate voltage drop waveforms at each cell instance. The instance-based dynamic waveforms facilitate accurate analysis of the power noise impact on chips' timing, and the ability to determine the precise amount and location of decoupling capacitance, as well as wire fixing that is needed. Typically, the transient simulation voltage waveforms are within 2% of SPICE and measured silicon.

RedHawk-EV supports a database technique that essentially eliminates the design capacity limitation, so that designers can trade off run-time performance with the physical memory size of their machine. Based on the available memory space, RedHawk automatically loads the database from cache, as needed, for high-capacity high-performance analysis and verification. By using RedHawk, designers are able to perform full-chip dynamic analysis in the same amount of time it takes to run traditional static IR-drop analysis.

Vectorless Dynamic and Extended Power Space Coverage

RedHawk provides extended power space exploration to broaden the coverage and accurately pinpoint the location of physical design weaknesses. RedHawk's innovative Vectorless Dynamic technology, with correlation results within 5% of SPICE, computes the statistical worst-case switching scenarios and event sequences for peak dynamic voltage drop without requiring a VCD file or user-provided vectors. In determining the cause of the dynamic "hot-spots", RedHawk’s technology considers:

Power-based constraints within a STA driven timing window
Power/ground network structural weaknesses
Timing conditions such as slack and critical paths

By accurately pinpointing the location of physical design weaknesses and determining their impact on dynamic voltage drop and ground bounce, designers can not only verify potential power-related functional and timing issues, but can also avoid excessive over-design.

Automatic Noise Repair through Grid Fixing and Decap Placement

Once the dynamic "hot spots" are identified and their cause determined, RedHawk, with optional Fix and Optimize (FAO) technology, automatically repairs the source of noise by either fixing the grid or placing decap protections or both. Traditionally, designers over-design the grid and fill all the empty cells with decoupling capacitance (decap) to reduce the risk of power supply noise related issues close to tape-out. But at 90nm and especially at 65nm and below processes, designers can no longer afford to guard band their designs. Decaps placed too far from the source of the noise does little in reducing the dynamic noise, while ineffective decaps can increase the total leakage current in the design, creating additional power integrity issues.

RedHawk with FAO provides accurate grid optimization and repair capability at the full-chip and at the regional level. Without compromising the total voltage drop, RedHawk increases metal resources in the areas of dynamic "hot spots", while reducing the metal widths of the areas with low voltage drop to avoid over-designing. RedHawk's non-uniform grid optimization allows designers to specify constraints such as area, metal layers, and target drop to be considered for optimization. Since the optimization engine is tightly integrated with RedHawk's proven dynamic analysis engine, the designers can feel confident with the accuracy of the optimized grid.

Along with grid optimization, RedHawk with FAO technology provides decap placement advisory for reducing dynamic voltage drop. Since decaps serve as local reservoirs of charge, their placement should be targeted such that they effectively reduce power and ground noise without adding unnecessary leakage current. RedHawk intelligently places decaps by considering the simultaneous switching effects, as well as removes unnecessary decaps that contribute to overall leakage current. RedHawk offers both decap advisory and repair - when in the advisory mode, it provides feedback to the designers on where decaps should be placed; and when in the repair mode, it places decaps to reduce the dynamic "hot spots". RedHawk's decap advisory and placement capability is based on its accurate dynamic power analysis engine with feedback to timing.

Unified Analysis and Debugging Environment

RedHawk provides a single unified environment for analysis and debugging of power, noise, and timing. Its layout based GUI provides designers with the flexibility and robustness required for easy-to-use yet comprehensive debugging capabilities.

From within the RedHawk environment, designers can access various views of their design, including layout view of the power density, instance power, and dynamic voltage drop. RedHawk also provides a number of waveform views such as total current and charge profile and instance-based Vdd drop and Vss ground bounce. Its full-chip movie mode playback with instance-based voltages over time assists designers in gaining access to critical information required to analyze and debug their designs.

RedHawk Power Closure Flow

RedHawk delivers complete power closure flow from prototyping to sign-off. Not only does RedHawk identify the location of dynamic "hot spots", it determines the cause of the problem by accurately pinpointing the power/ground network weaknesses, and assists in repairing the sources of noise. RedHawk takes power integrity analysis and verification to the next level by offering solutions that enable designers to quickly reach power closure.