PowerTheater

PowerTheater - Low Power Design & Power Analysis For Nanometer System-on-Chip Design

Power Theater is a comprehensive set of power tools that help you create maximum power efficiency for your SoC designs. Apache is the only company delivering power software focused at the architectural, RT and gate levels of abstraction.

Key Features:

SoC RTL Power Analysis
Analyze power consumption early in the design flow to check the power budget and direct power reduction efforts
Low-power RTL design
Perform power analysis as RTL blocks are being designed, including Zerosim vectorless capability to perform architecture tradeoffs
Handle clock, memory, data path control logic and I/O
See the simultaneous impact of all the components in a full-chip design
De facto industry standard for RTL power design
High-performance, high-capacity full-chip power analysis, including peak and timebased analysis, vector coverage analysis and power optimization
Complete HDL coverage for SoC design
Support for Verilog, Verilog2001, VHDL and mixed language environments in one-pass
Versatile graphical analysis environment
View power analysis results and optimization trade-offs quickly, and intuitively produce the most power-efficient designs possible
Accurate gate-level power verification
Provides precise assessment of chip power behavior either average or time based, including SPEF back-annotation, built-in slew calculator and support for hierarchical design flows
Integration with CoolTime from Apache
Determine the critical clock cycle for dynamic voltage drop analysis and feed forward initial starting conditions for CoolTime

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