Webinars

Chip-Package Co-Design: Applying Chip Power Model in System Power Integrity Analysis
Location: At Your Desk
May 8, 2008 (Archive)

Power, noise, and reliability is one of the critical design challenges for system engineers today, Shrinking geometry, increasing functionality, higher input-output (I/O) signaling speed, low-power / low-leakage design techniques, and advanced packaging technologies such as system-in-package (SiP) exacerbate management of power, noise, and reliability challenges. What's required is a chip-package co-design methodology that enables co-analysis and co-optimization across chip, package, and system with package-aware IC and IC-aware package / system solutions.

In this webinar, Apache Design Solutions will explore proven chip-package co-design methodology followed by application examples. The presentation will discuss co-design methodology based on a chip power model (CPM) that accurately represents the switching noise of the die's power delivery network. The presentation will demonstrate how CPM can be used during early stage prototyping to optimize package/board designs resulting in the most cost effective products. The presentation will include other applications on ways to control system timing variation due to power supply noise and jitter and discuss the types of system failure that are detected, such as system-level DDR jitter issue, and how the solution allows designers to analyze and fix problems prior to tape-out.

• Chip power integrity with impact of package and board
• Early system prototyping with accurate chip power model
• Methodology for chip-aware package analysis and optimization

• Physical designers working on designs especially at 90nm or below
• Signal integrity engineers
• Package and system power deliver network design engineers
• Design methodology and design architects
  

Towards True Co-Design: Bridging the Gap between IC and Package design for Power Integrity
Location: At Your Desk
October 9, 2007 (Archive)

For many years, the need for chip-package co-design to rapidly meet increasingly tight signal and power integrity (SI/PI) constraints in a cost-effective way has been more than obvious. However, "Co-design" as it is practiced today, is often little more than isolated design of the chip and package followed by co-optimization across product generations. Existing EDA tools and analysis techniques address SI/PI issues at the package and chip levels, but not with an integrated approach, which is needed for accurate and actionable tradeoff analyses.

In this webinar, Apache Design Solutions and Optimal Corporation will explore the symmetrical use of package-aware chip analysis and chip-aware package analysis to address true IC-Package co-design. The chip-package core power delivery network (PDN) is analyzed for static IR drop and dynamic voltage drop (DvD), pointing to design improvements through floor planning, decoupling capacitance, and wire-bonding design. Including the I/O subsystem as well enables assessment of timing metrics (e.g. jitter) and simultaneous switching output (SSO) noise, pointing to design improvements available through voltage domain partitioning and impedance control. Due to the unique awareness of both the chip and package, tradeoffs in chip versus package complexity emerge as a new design freedom to meet performance and cost demands.

• Impact of package on chip power integrity
• Methodology for power analysis with consideration of package impact
• Technology for generating core power delivery network
• Use of chip power model in package design

• Physical designers working on designs especially at 90nm or below
• Signal integrity engineers
• Package design engineers
• Design methodology and design architects