Press Release

Apache to Present Technical Webinar on Chip-Package Co-design Methodology

MOUNTAIN VIEW, Calif. –May 5, 2008 - Apache Design Solutions, the technology leader in power, noise, and reliability (PNR) signoff for chip, package, and system designs, today announced that the company will present an online technical webinar entitled “Chip-Package Co-Design: Applying Chip Power Model in System Power Integrity Analysis.” Apache will detail the methodology used for integrated chip-package co-design based on a Chip Power Model (CPM), as well as design examples to demonstrate application and results.

The live webinar will be broadcast via TechOnLine:

Thursday, May 8, 2008
11:00 a.m. PST, 2:00 p.m. EST
Register at http://www.techonline.com/learning/webinar/207200568

Power, noise, and reliability are critical design challenges for system engineers today, Shrinking geometry, increasing functionality, higher input-output (I/O) signaling speed, low-power / low-leakage design techniques, and advanced packaging technologies such as system-in-package (SiP) exacerbate management of power, noise, and reliability challenges. The webinar will discuss co-design methodology and CPM, an accurate model of the die’s power delivery network (PDN) switching noise. It will demonstrate how CPM can be used during early stage prototyping to optimize package/board designs, resulting in the most cost effective products. Highlights include:

Chip power integrity and its impact of package and board
Early system prototyping with accurate chip power model
Methodology for IC-aware package analysis and optimization

Apache Design Solutions, NSPICE, RedHawk, PakSi-E, PakSi-TM, PsiWinder, Sahara, Sentinel, and Vectorless Dynamic are trademarks of Apache Design Solutions, Inc.

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