Executive Team

Andrew T. Yang co-founded Apache in 2001, focusing on power closure for advanced high-performance and low-power SoC designs, and has served as chief executive officer and chairman of the board of directors since its inception. Dr. Yang has been an active entrepreneur and investor in EDA since 1993, when he founded Anagram, a high-capacity simulation solutions provider for deep-submicron ICs. Anagram merged with Avant! in 1996, where he served as the Vice President of the Analysis Product Division responsible for all extraction and analysis products until 1998. Since 1998, Dr. Yang was a lead investor and a director of a number of EDA start-ups including CADMOS (now Cadence), Ultima (now Cadence), InnoLogic (now Synopsys), and Mojave (now Magma). Dr. Yang received his Ph.D. from the University of Illinois, Urbana-Champaign in 1989 and was a tenured professor at the University of Washington from 1989 to 1996.

Prior to joining Apache, Dr. Yang co-founded InnoLogic Systems, a provider of formal verification solutions for full-custom designs. InnoLogic was acquired by Synopsys in 2003, where he continued to lead the adoption, integration, and advancement of the InnoLogic products as a senior director in the implementation business unit. Previous to InnoLogic, Dr. Yang held various management positions in SGI/MIPS, LSI, and Avant!. Dr. Yang has extensive experience in development and management of EDA software, including memory compilers, static timing tools, DFT and functional verification solutions. He received his Ph.D. and M.S. in Computer Science from Stanford University and a B.S. degree from Shanghai University of Science and Technology.

Shen Lin co-founded Apache along with Andrew T. Yang and Norman Chang in March 2001. Before founding Apache, Dr. Lin worked at Palo Alto HP Labs, focusing on inductance related signal integrity issues and contributing to the HP-Intel IA64 micro-processor design. In 2000, he co-authored a widely read book on state-of-the-art methods for interconnect titled "Interconnect Analysis and Synthesis", published by John Wiley & Sons. Prior to his work at HP Labs, Dr. Lin worked at LSI Logic developing on-the-fly ASIC design methodologies. His career began as a research staff member of the IBM T. J. Watson Research Center in Yorktown Heights, New York, focusing on fast circuit simulation and clock-skew minimization techniques. Dr. Lin received his Ph.D. in EECS from the University of California, Berkeley in 1992, where he published his well-known thesis on recursive convolution for circuit simulation.

Prior to joining Apache, Mr. Shirley was vice president of worldwide sales and support at Jasper Design Automation. Previous to Jasper, Mr. Shirley was vice president of North American Sales at Verisity Design, Inc. (now a Cadence company), where he built and managed a sales team of over 50 people, targeting the domestic proliferation of the company's functional verification solutions at major accounts. Previous to Verisity, Mr. Shirley held various sales and sales management positions at Avant!, Aspect Development, Quickturn Design Systems, Ready Systems Corporation and Viewlogic Systems. Mr. Shirley began his EDA career at Intergraph Corporation, as an applications engineer. Mr. Shirley holds a Bachelors degree in Computer Engineering from Auburn University in Auburn, AL, where he graduated with honors.

Mr. Sarkar joined Apache as a Senior Applications Engineer in 2003. Since then he has taken on different roles and responsibilities inside Apache including his previous role of Director of Product Engineering. Prior to joining Apache, Mr. Sarkar worked for several years in Sun Microsystems on several generations of UltraSparc processors. He also held engineering positions at Cadence and National Semiconductor Corp. He holds a B.Tech from the Indian Institute of Technology, Kanpur, a MS EE from Oregon State University, and a MBA from Santa Clara University.